From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: devi priya <quic_devipriy@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, jassisinghbrar@gmail.com,
catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org,
arnd@arndb.de, marcel.ziswiler@toradex.com,
nfraprado@collabora.com, broonie@kernel.org,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: quic_srichara@quicinc.com, quic_gokulsri@quicinc.com,
quic_sjaganat@quicinc.com, quic_kathirav@quicinc.com,
quic_arajkuma@quicinc.com, quic_anusha@quicinc.com,
quic_poovendh@quicinc.com
Subject: Re: [PATCH 2/6] clk: qcom: ipq9574: Enable APSS clock driver
Date: Tue, 31 Jan 2023 11:29:26 +0200 [thread overview]
Message-ID: <c51ab88e-d568-8322-093e-b82f11f63a0b@linaro.org> (raw)
In-Reply-To: <20230113143647.14961-3-quic_devipriy@quicinc.com>
On 13/01/2023 16:36, devi priya wrote:
> Enable APSS clock driver for IPQ9574 based devices
>
> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
> drivers/clk/qcom/apss-ipq-pll.c | 13 +++++++++++++
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
Note, the drivers/mailbox isn't a part of the 'drivers/clk', so it
should go to a separate patch (and it will be handled by a different
maintainer).
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index a5aea27eb867..dd0c01bf5a98 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -61,6 +61,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
> .test_ctl_hi_val = 0x4000,
> };
>
> +static const struct alpha_pll_config ipq9574_pll_config = {
> + .l = 0x3b,
> + .config_ctl_val = 0x200D4828,
> + .config_ctl_hi_val = 0x6,
> + .early_output_mask = BIT(3),
> + .aux2_output_mask = BIT(2),
> + .aux_output_mask = BIT(1),
> + .main_output_mask = BIT(0),
> + .test_ctl_val = 0x0,
> + .test_ctl_hi_val = 0x4000,
> +};
> +
> static const struct regmap_config ipq_pll_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -102,6 +114,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
> static const struct of_device_id apss_ipq_pll_match_table[] = {
> { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
> { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
> + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_config },
> { }
> };
> MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 0e9f9cba8668..90e74f9d7cb3 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
> .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
> };
>
> +static const struct qcom_apcs_ipc_data ipq9574_apcs_data = {
> + .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
> +};
As the data is identical to ipq6018's one, please don't add a duplicate
of it.
> +
> static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
> .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
> };
> @@ -143,6 +147,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
> static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
> { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
> + { .compatible = "qcom,ipq9574-apcs-apps-global", .data = &ipq9574_apcs_data },
> { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
> { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
> { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
--
With best wishes
Dmitry
next prev parent reply other threads:[~2023-01-31 9:29 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 14:36 [PATCH 0/6] Add APSS clock controller support for IPQ9574 devi priya
2023-01-13 14:36 ` [PATCH 1/6] dt-bindings: clock: Add YAML schemas for QCOM A73 PLL devi priya
2023-01-13 14:57 ` Krzysztof Kozlowski
2023-01-27 15:37 ` Devi Priya
2023-01-13 15:05 ` Konrad Dybcio
2023-01-27 15:40 ` Devi Priya
2023-01-13 14:36 ` [PATCH 2/6] clk: qcom: ipq9574: Enable APSS clock driver devi priya
2023-01-13 15:12 ` Konrad Dybcio
2023-01-27 15:43 ` Devi Priya
2023-01-31 9:29 ` Dmitry Baryshkov [this message]
2023-01-31 9:39 ` Devi Priya
2023-01-13 14:36 ` [PATCH 3/6] arm64: defconfig: Enable ipq6018 apss clock and PLL controller devi priya
2023-01-31 9:31 ` Dmitry Baryshkov
2023-02-01 14:26 ` Devi Priya
2023-01-13 14:36 ` [PATCH 4/6] arm64: dts: qcom: ipq9574: Add support for APSS clock controller devi priya
2023-01-13 14:36 ` [PATCH 5/6] dt-bindings: mailbox: Add compatible for IPQ9574 devi priya
2023-01-13 15:00 ` Krzysztof Kozlowski
2023-01-13 15:13 ` Konrad Dybcio
2023-01-27 15:45 ` Devi Priya
2023-01-13 14:36 ` [PATCH 6/6] clk: qcom: Fix APSS PLL and RCG Configuration devi priya
2023-01-13 15:20 ` Konrad Dybcio
2023-01-13 16:17 ` Robert Marko
2023-01-31 9:23 ` Devi Priya
2023-01-31 9:17 ` Devi Priya
2023-01-31 9:40 ` Dmitry Baryshkov
2023-02-01 14:40 ` Devi Priya
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