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Thu, 27 Jun 2024 14:37:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 104064002D; Thu, 27 Jun 2024 14:37:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3B7BA2171FF; Thu, 27 Jun 2024 14:36:47 +0200 (CEST) Received: from [10.48.86.79] (10.48.86.79) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 27 Jun 2024 14:36:46 +0200 Message-ID: Date: Thu, 27 Jun 2024 14:36:46 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board To: Marek Vasut , CC: Christophe Roullier , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , , , References: <20240623195233.81550-1-marex@denx.de> Content-Language: en-US From: Alexandre TORGUE In-Reply-To: <20240623195233.81550-1-marex@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-27_08,2024-06-27_03,2024-05-17_01 Hi Marek On 6/23/24 21:51, Marek Vasut wrote: > Add ethernet support for the DH STM32MP13xx DHCOR DHSBC carrier board. > This carrier board is populated with two gigabit ethernet ports and two > Realtek RTL8211F PHYs, both are described in this DT patch. > > Signed-off-by: Marek Vasut > --- > Cc: Alexandre Torgue > Cc: Christophe Roullier > Cc: Conor Dooley > Cc: Krzysztof Kozlowski > Cc: Maxime Coquelin > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-stm32@st-md-mailman.stormreply.com > --- > .../boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts > index 5f4f6b6e427a5..bacb70b4256bc 100644 > --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts > +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts > @@ -22,6 +22,8 @@ / { > "st,stm32mp135"; > > aliases { > + ethernet0 = ðernet1; > + ethernet1 = ðernet2; > serial2 = &usart1; > serial3 = &usart2; > }; > @@ -72,6 +74,60 @@ channel@12 { > }; > }; > Kernel bot issue was linked to a dependency with Christophe Roullier patches which introduced ethernet1/2 on stm32mp131.dtsi. Those patches have been merged on stm32-next, so no more issues with yours. So: Applied on stm32-next. Cheers Alex > +ðernet1 { > + phy-handle = <ðphy1>; > + phy-mode = "rgmii-id"; > + pinctrl-0 = <ð1_rgmii_pins_a>; > + pinctrl-1 = <ð1_rgmii_sleep_pins_a>; > + pinctrl-names = "default", "sleep"; > + st,ext-phyclk; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + ethphy1: ethernet-phy@1 { > + /* RTL8211F */ > + compatible = "ethernet-phy-id001c.c916"; > + interrupt-parent = <&gpiog>; > + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; > + reg = <1>; > + reset-assert-us = <15000>; > + reset-deassert-us = <55000>; > + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; > + }; > + }; > +}; > + > +ðernet2 { > + phy-handle = <ðphy2>; > + phy-mode = "rgmii-id"; > + pinctrl-0 = <ð2_rgmii_pins_a>; > + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; > + pinctrl-names = "default", "sleep"; > + st,ext-phyclk; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + ethphy2: ethernet-phy@1 { > + /* RTL8211F */ > + compatible = "ethernet-phy-id001c.c916"; > + interrupt-parent = <&gpiog>; > + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; > + reg = <1>; > + reset-assert-us = <15000>; > + reset-deassert-us = <55000>; > + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; > + }; > + }; > +}; > + > &gpioa { > gpio-line-names = "", "", "", "", > "", "DHSBC_USB_PWR_CC1", "", "",