From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C73522C21D0; Wed, 14 Oct 2026 10:22:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791973355; cv=none; b=WdrBUWhESKBekUZmnyExKItt6cKe1Fu0v7THeg2koX/glSI/BbsbMAwaYfsOFVfwJD77ZB4GjcRXYsvKKKUSzIOiRvGsbj+bPyU2zMD7GFBbxeUxMzzxKwCkfJPCGA2AFYVn9Hx9fpJnGgm8HQMbMdY6vIJyEftx3ADdNPEUtA4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791973355; c=relaxed/simple; bh=1ESQ0ekRio6WEiqPpZNuXzRCMorhN8/L6m7ea8uJC8s=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=arGmyB1fV9HDauVQVUCXqEzW3pm2KmO7lUfT2FWs4kl4HTrWXGGo83RvDZB+ciXxwhvTPpnx4BbEnPEGZnRQrQPDBaboD+dFhbDcsyKxbAc3qRTJ8ceNgSt4MuuP22muHoclezQpUEzeve0BNgQk5L709D5+7riP4IX90ARRk3M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K2kM6Zga; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K2kM6Zga" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B0CA1F00898; Wed, 14 Oct 2026 10:22:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791973354; bh=HFwvdFjQOwo7pNUIA7Q1LUEaShtAWaPIThtJF3QfRdg=; h=Date:Subject:From:To:Cc:References:In-Reply-To; b=K2kM6Zga5EhfcsonE7sl3EtIK834t52YBu16IpCI54NiHzwbxmjsop6jsIk4seoj3 njJaiBnWL97Mky0phu1y9UjhuwQz43S++fXQhFTaqOCvAt5Y3CWHlddrdzcOw4HvQD OwRSsDgQeM+ImnftFCyosIEzLm06LF+Sw8A+uwibe47IxbaAp1crYzv0TRWkLhUuZ/ sjaXy5f2p2dVFmncemOue2KWkbbi1T8ySgYR7sjjr9HJDJadx3FE8ysaARLs/ShGJ7 QObrWjZpdlAaIqiSwA5p4QBsUx2sfobMcSd4UIn/jSIi6ioVDd/WsGsm+EarAFiRTP 5VWMjU8ncMtNQ== Message-ID: Date: Wed, 14 Oct 2026 12:22:25 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: introduce toshiba,tc9564-msigen.yaml From: Krzysztof Kozlowski To: Conor Dooley Cc: Alex Elder , tglx@kernel.org, radu@rendec.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, danielt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Thompson References: <20261012190245.3988619-1-elder@riscstar.com> <20261012190245.3988619-2-elder@riscstar.com> <20261013-coexist-sixtyfold-cc6614086d3a@spud> <20261014-eminent-normal-lynx-3ebba3@quoll> Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 14/10/2026 12:15, Krzysztof Kozlowski wrote: > On Tue, Oct 13, 2026 at 06:54:11PM +0100, Conor Dooley wrote: >> On Mon, Oct 12, 2026 at 02:02:43PM -0500, Alex Elder wrote: >>> Define the binding for the MSIGEN interrupt controller present in the >>> Toshiba TC9564 SoC. >>> >>> Co-developed-by: Daniel Thompson >>> Signed-off-by: Daniel Thompson >>> Signed-off-by: Alex Elder >>> --- >>> .../toshiba,tc9564-msigen.yaml | 70 +++++++++++++++++++ >>> MAINTAINERS | 6 ++ >>> 2 files changed, 76 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml b/Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml >>> new file mode 100644 >>> index 0000000000000..39dc63964bd52 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml >>> @@ -0,0 +1,70 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/interrupt-controller/toshiba,tc9564-msigen.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Toshiba TC9564 MSIGEN Interrupt Controller >>> + >>> +maintainers: >>> + - Daniel Thompson >>> + - Alex Elder >>> + >>> +description: | >>> + The Toshiba TC9564 is an SoC accessed by a host system through the >>> + upstream PCIe port on the PCIe switch it implements. The switch >>> + includes an embedded PCIe endpoint that provides access to various >>> + SoC peripherals (including an interrupt controller) via its BARs. >>> + >>> + The TC9564 MSIGEN (MSI Generator) provides an interrupt controller >>> + with 25 hardware interrupt lines. It aggregates internal interrupts >>> + and generates a single PCIe MSI to the host. Each PCIe function >>> + implements an MSIGEN instance. >>> + >>> + Each MSIGEN uses a gated clock and reset line. These are provided >>> + by the clock and reset controllers internal to the TC9564. >>> + >>> +allOf: >>> + - $ref: /schemas/interrupt-controller.yaml# >>> + >>> +properties: >>> + compatible: >>> + const: toshiba,tc9564-msigen >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + interrupt-controller: true >>> + >>> + '#interrupt-cells': >>> + const: 1 >>> + >>> + clocks: >>> + maxItems: 1 >>> + description: Gate clock from the TC9564 clock controller >> >> I'm surprised that the clock is not mandatory.. Realistically the reset >> is also mandatory, there's probably one instance of this on the device, >> where both clock and reset are connected. I'd add both to the required >> list. >> >> Otherwise this looks >> fine to me. I know you mentioned this device in the other series that >> we were discussing but I don't see how it is related and is perfectly >> fine to implement as a standalone device as you have done here. > > I still do not understand why do we need to describe the inner wirings > of the tc9564 device. So far I found no posting of DTS showing proper > usage of it on the host. Without proper usage, what is the point exactly > to describe the inner specifics of tc9564? And as shown here: https://lore.kernel.org/all/20261012152408.3729237-5-elder@riscstar.com/ there is no single user of any of this (this=reset, clock, irqchip probably and more) in upstreamed patches. I am getting tired to keep discussing it, so next time instead of words, please post CODE which is the argument - who uses any of these devices you keep adding. Best regards, Krzysztof