From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84CEC1624DD for ; Fri, 6 Jun 2025 23:03:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749251004; cv=none; b=fQlu32SIglLzteRlupyzS5G0nIlhCI7ElNUPoB1Dez+jcbkYzdOSNCtBo/d5NySg61P3DLN0HVGJK74WZYTU+1YzDg1jNwatD/X0Z0iFqPRmnyT9N9B/jGuUMTMe0jrmO7zHZm4k6L06l1pxOfwccS/tT+9lswjYxM1jcxt+gx8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749251004; c=relaxed/simple; bh=csUroKj9iOCj4e1J07ZIsTgzNuIPvxUlRDMg6n8M/cA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IKPQoO898huOH8WS1rvaxUsZDcXKmD68s9cp3stvmCqBVLcVHDQ6x1TbUFkuboleTK5uhlOlWvIbydJa8YbSFEIomaTYtvfWrFrEbU9v8myju/eWXDir0qHRrPElBnb2Q8KuC+s/ldjUM8XfXCimEUUvOixnBzRkgKRu7LxXvvQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Ptcayhb+; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Ptcayhb+" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1749251000; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nl7fH6FNDtu/VqccuBmnAP9vsS3V71ySkYYbHAfw7Z8=; b=Ptcayhb+lXXE5AuLIZjs/q8BjRUSzgSgWMO5q3SDOUX2Lccj1czWKaPIUsRksdZ9KsZmzG ubgIaEdvwkIVvJybGF/ET1D6xCgemRRxnJA+aAFT6vUQiIg9khxBC9L7yKnAL28r+UMJDo /JRMcULVbSeXfBUujXlpLduKFRkjL2A= Date: Fri, 6 Jun 2025 16:03:08 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v4 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings To: Anup Patel , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250525084710.1665648-1-apatel@ventanamicro.com> <20250525084710.1665648-13-apatel@ventanamicro.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Atish Patra In-Reply-To: <20250525084710.1665648-13-apatel@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 5/25/25 1:46 AM, Anup Patel wrote: > Add device tree bindings for the RPMI system MSI service group > based interrupt controller for the supervisor software. > > The RPMI system MSI service group is defined by the RISC-V > platform management interface (RPMI) specification. > > Signed-off-by: Anup Patel > --- > .../riscv,rpmi-system-msi.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml > new file mode 100644 > index 000000000000..ac13cec0666e > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V RPMI system MSI service group based interrupt controller > + > +maintainers: > + - Anup Patel > + > +description: | > + The RISC-V Platform Management Interface (RPMI) [1] defines a > + messaging protocol which is modular and extensible. The supervisor > + software can send/receive RPMI messages via SBI MPXY extension [2] > + or some dedicated supervisor-mode RPMI transport. > + > + The RPMI specification [1] defines system MSI service group which > + allow application processors to receive MSIs upon system events > + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug > + event, memory hotplug event, etc from the platform microcontroller. > + The supervisor software can access RPMI system MSI service group via > + SBI MPXY channel or some dedicated supervisor-mode RPMI transport. > + > + =========================================== > + References > + =========================================== > + > + [1] RISC-V Platform Management Interface (RPMI) > + https://github.com/riscv-non-isa/riscv-rpmi/releases > + > + [2] RISC-V Supervisor Binary Interface (SBI) > + https://github.com/riscv-non-isa/riscv-sbi-doc/releases > + nit: Same comment as previous patch. > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + description: > + Intended for use by the supervisor software. > + const: riscv,rpmi-system-msi > + > + mboxes: > + maxItems: 1 > + description: > + Mailbox channel of the underlying RPMI transport or SBI message proxy channel. > + > + msi-parent: true > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 1 > + > +required: > + - compatible > + - mboxes > + - msi-parent > + - interrupt-controller > + - "#interrupt-cells" > + > +additionalProperties: false > + > +examples: > + - | > + interrupt-controller { > + compatible = "riscv,rpmi-system-msi"; > + mboxes = <&mpxy_mbox 0x2000 0x0>; > + msi-parent = <&imsic_slevel>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > +... Otherwise, LGTM. Reviewed-by: Atish Patra