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[83.9.29.26]) by smtp.gmail.com with ESMTPSA id er14-20020a05651248ce00b004fb844a03c7sm211188lfb.186.2023.07.06.04.18.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Jul 2023 04:18:16 -0700 (PDT) Message-ID: Date: Thu, 6 Jul 2023 13:18:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v1 6/6] arm64: dts: qcom: sa8775p-ride: enable pcie nodes Content-Language: en-US To: Mrinmay Sarkar , agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <1688545032-17748-1-git-send-email-quic_msarkar@quicinc.com> <1688545032-17748-7-git-send-email-quic_msarkar@quicinc.com> From: Konrad Dybcio In-Reply-To: <1688545032-17748-7-git-send-email-quic_msarkar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 5.07.2023 10:17, Mrinmay Sarkar wrote: > Enable pcie0, pcie1 nodes and their respective phy's. > > Signed-off-by: Mrinmay Sarkar > --- grep for '&[a-z0-9]\{' and please fix all missing spaces before the opening braces. Konrad > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 68 +++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index ab767cfa51ff..4a39294259fe 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -443,6 +443,74 @@ qup_uart17_rx: qup0-uart17-rx-pins { > bias-pull-down; > }; > }; > + > + pcie0_default_state: pcie0-default { > + perst { > + pins = "gpio2"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + clkreq { > + pins = "gpio1"; > + function = "pcie0_clkreq"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + wake { > + pins = "gpio0"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + pcie1_default_state: pcie1-default { > + perst { > + pins = "gpio4"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + clkreq { > + pins = "gpio3"; > + function = "pcie1_clkreq"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + wake { > + pins = "gpio5"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > +}; > + > +&pcie0{ > + status = "okay"; > +}; > + > +&pcie1{ > + status = "okay"; > +}; > + > +&pcie0_phy{ > + vdda-phy-supply = <&vreg_l5a>; > + vdda-pll-supply = <&vreg_l1c>; > + > + status = "okay"; > +}; > + > +&pcie1_phy{ > + vdda-phy-supply = <&vreg_l5a>; > + vdda-pll-supply = <&vreg_l1c>; > + > + status = "okay"; > }; > > &uart10 {