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Tue, 24 Jun 2025 06:28:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHhSkFmD+5UXG4jGrsUbcWVvnGV+HYRoYvsylLGuSpLZ0cZAFjd7dWnoz7KErNAGSRJxIUwtQ== X-Received: by 2002:a05:6a00:3e0b:b0:747:bd28:1ca1 with SMTP id d2e1a72fcca58-7490d663700mr28575577b3a.3.1750771699195; Tue, 24 Jun 2025 06:28:19 -0700 (PDT) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-749c882f5b8sm1961515b3a.95.2025.06.24.06.28.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jun 2025 06:28:18 -0700 (PDT) Message-ID: Date: Tue, 24 Jun 2025 18:58:09 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V6 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC To: Neil Armstrong , jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski@linaro.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, quic_kamalw@quicinc.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_skakitap@quicinc.com, stephan.gerhold@linaro.org References: <20250509110959.3384306-1-jishnu.prakash@oss.qualcomm.com> <20250509110959.3384306-4-jishnu.prakash@oss.qualcomm.com> <8736dea0-2a5b-49d8-8445-239e5d11174e@linaro.org> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <8736dea0-2a5b-49d8-8445-239e5d11174e@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=NdDm13D4 c=1 sm=1 tr=0 ts=685aa7f4 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Bk9QF8R_Bm2aD44dtyUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDExMyBTYWx0ZWRfX4koZf2BQdcdr 6PoROdAs4xeJUj+vupefJxDJ+a86ySaNwUVY6FvFhuUCAa6WBye+co3OPGx46V7cb1O+tpyoNCg +ZSQnQf5eX4SpWLO3U/k6a5gn2GpuXY8oF+iRhxjjyw3OAJtYneLoGPjVvN022vy9Bsaa2poEtW gmIWOfFRK7BbCBJdcHLTdrSVS/zSJzKlopWx02uh/VZwxHJqBSUvYVCPKJKt+xDjQ0bpZyIuCPa flWX/tXs/FzJdTIsBJyrVmW22yZ/HHAhkAqO+AWhzu/VIAiaHI+pgAdw6+PpWwX4lskk/B1MHlV 0AEzkkLhqlpIw9tZsc2D/aWrP+zptsjWBYHsX8JPHGlg5qj0OWGq9InQbCNyZG98m1HiQwHP1zw yxBqJRlIBsuZgjKEg0StgBbWEM1FZ++XhUHTXXVO9YZr8lDaErlqqUOD3JiZqBG/bcE1pQSf X-Proofpoint-ORIG-GUID: -NsrosXk7nIVOcFhFRRbfmoaLP3cn-Dh X-Proofpoint-GUID: -NsrosXk7nIVOcFhFRRbfmoaLP3cn-Dh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_05,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240113 Hi Neil, On 5/9/2025 8:05 PM, neil.armstrong@linaro.org wrote: > > Hi, > On 09/05/2025 13:09, Jishnu Prakash wrote: >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >> >> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >> going through PBS(Programmable Boot Sequence) firmware through a single >> register interface. This interface is implemented on SDAM (Shared >> Direct Access Memory) peripherals on the master PMIC PMK8550 rather >> than a dedicated ADC peripheral. >> >> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC >> channels and virtual channels (combination of ADC channel number and >> PMIC SID number) per PMIC, to be used by clients of this device. > > The following is missing to allow it to be a qcom,spmi-pmic subnode: > > =========================><================================================ > diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml > index 11da55644262..b97f0e7b269e 100644 > --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml > +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml > @@ -127,6 +127,7 @@ patternProperties: >    "^adc@[0-9a-f]+$": >      type: object >      oneOf: > +      - $ref: /schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# >        - $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml# >        - $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml# >        - $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml# > =========================><================================================ > > Thanks, > Neil > Thanks for catching this, I'll add a patch for this in my next patch series. Although I tried running full dt_binding_check and dtbs_check in my local workspace with my three binding patches applied, I could not see any error related to this, I'm not sure why. Thanks, Jishnu >> >> Signed-off-by: Jishnu Prakash >> --- >> Changes since v5: