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Fri, 7 Apr 2023 10:21:25 GMT Received: from [10.216.18.47] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 7 Apr 2023 03:21:15 -0700 Message-ID: Date: Fri, 7 Apr 2023 15:51:12 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH V11 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and RDP433 variant Content-Language: en-US To: Marc Zyngier CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20230404101622.5394-1-quic_devipriy@quicinc.com> <20230404101622.5394-4-quic_devipriy@quicinc.com> From: Devi Priya In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tyNx0KBWHNmsGSGr_4E5QkhMMB__RRFu X-Proofpoint-ORIG-GUID: tyNx0KBWHNmsGSGr_4E5QkhMMB__RRFu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-07_06,2023-04-06_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 clxscore=1011 priorityscore=1501 impostorscore=0 mlxlogscore=707 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304070095 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 4/4/2023 4:33 PM, Marc Zyngier wrote: > On 2023-04-04 11:16, Devi Priya wrote: >> Add initial device tree support for Qualcomm IPQ9574 SoC and >> Reference Design Platform(RDP) 433 which is based on IPQ9574 >> family of SoCs >> >> Co-developed-by: Anusha Rao >> Signed-off-by: Anusha Rao >> Co-developed-by: Poovendhan Selvaraj >> Signed-off-by: Poovendhan Selvaraj >> Signed-off-by: Devi Priya >> --- >>  Changes in V11: >>     - Dropped the unused backup clock source bias_pll_ubi_nc_clk >> >>  arch/arm64/boot/dts/qcom/Makefile           |   1 + >>  arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts |  84 +++++++ >>  arch/arm64/boot/dts/qcom/ipq9574.dtsi       | 263 ++++++++++++++++++++ >>  3 files changed, 348 insertions(+) >>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi >> > > [...] > >> +        intc: interrupt-controller@b000000 { >> +            compatible = "qcom,msm-qgic2"; >> +            reg = <0x0b000000 0x1000>,  /* GICD */ >> +                  <0x0b002000 0x1000>,  /* GICC */ > > This is definitely wrong. The GICC region cannot be less than > 8kB, as the GICC_DIR register is in the second 4kB region. > > I'm pretty sure the kernel shouts at you when booting at EL2. Got it, will update the size to 8kB > >> +                  <0x0b001000 0x1000>,  /* GICH */ >> +                  <0x0b004000 0x1000>;  /* GICV */ > > Same thing here. okay > >> +            #address-cells = <1>; >> +            #size-cells = <1>; >> +            interrupt-controller; >> +            #interrupt-cells = <3>; >> +            interrupts = ; > > Missing target CPU encoding. Okay, will update the interrupts as below. Hope this is the expectation? Please let us know if we are missing something interrupts = ; > >         M. Best Regards, Devi Priya