From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC Date: Wed, 13 Feb 2019 16:11:38 +0900 Message-ID: References: <20190212175052.6310-1-krzk@kernel.org> <20190212175052.6310-4-krzk@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190212175052.6310-4-krzk@kernel.org> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Krzysztof Kozlowski , Rob Herring , Mark Rutland , Kukjin Kim , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org List-Id: devicetree@vger.kernel.org Hi, On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote: > Add the gate clock for ADC block on Exynos5410. > > Signed-off-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos5410.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c > index 0a0b09591e6f..b2da2c8fa0c7 100644 > --- a/drivers/clk/samsung/clk-exynos5410.c > +++ b/drivers/clk/samsung/clk-exynos5410.c > @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { > GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), > GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), > GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), > + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), > GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), > > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", > I checked it on Exynos5410 TRM. Looks good to me. Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Samsung Electronics