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X-CSE-ConnectionGUID: c4nys7iCQhSEjg28/63XYw== X-CSE-MsgGUID: knrB/t/5TE6ckMB8gDY8sA== X-IronPort-AV: E=McAfee;i="6700,10204,11103"; a="26366574" X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="26366574" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 05:32:12 -0700 X-CSE-ConnectionGUID: tdkimbqMR1mmScCfKZcLzg== X-CSE-MsgGUID: KkhV+DFFQ7q2xccIm4rZzw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="40414794" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.222]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 05:32:04 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Fri, 14 Jun 2024 15:32:01 +0300 (EEST) To: Krishna chaitanya chundru cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?ISO-8859-2?Q?Krzysztof_Wilczy=F1ski?= , Bjorn Helgaas , johan+linaro@kernel.org, bmasney@redhat.com, djakov@kernel.org, Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, LKML , linux-pci@vger.kernel.org, vireshk@kernel.org, quic_vbadigan@quicinc.com, quic_skananth@quicinc.com, quic_nitegupt@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org Subject: Re: [PATCH v14 3/4] PCI: Bring the PCIe speed to MBps logic to new pcie_link_speed_to_mbps() In-Reply-To: <20240609-opp_support-v14-3-801cff862b5a@quicinc.com> Message-ID: References: <20240609-opp_support-v14-0-801cff862b5a@quicinc.com> <20240609-opp_support-v14-3-801cff862b5a@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Sun, 9 Jun 2024, Krishna chaitanya chundru wrote: > Bring the switch case in pcie_link_speed_mbps() to new function to > the header file so that it can be used in other places like > in controller driver. > > Signed-off-by: Krishna chaitanya chundru > Reviewed-by: Manivannan Sadhasivam > Acked-by: Bjorn Helgaas > --- > drivers/pci/pci.c | 19 +------------------ > drivers/pci/pci.h | 22 ++++++++++++++++++++++ > 2 files changed, 23 insertions(+), 18 deletions(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index d2c388761ba9..6e50fa89b913 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -6027,24 +6027,7 @@ int pcie_link_speed_mbps(struct pci_dev *pdev) > if (err) > return err; > > - switch (to_pcie_link_speed(lnksta)) { > - case PCIE_SPEED_2_5GT: > - return 2500; > - case PCIE_SPEED_5_0GT: > - return 5000; > - case PCIE_SPEED_8_0GT: > - return 8000; > - case PCIE_SPEED_16_0GT: > - return 16000; > - case PCIE_SPEED_32_0GT: > - return 32000; > - case PCIE_SPEED_64_0GT: > - return 64000; > - default: > - break; > - } > - > - return -EINVAL; > + return pcie_link_speed_to_mbps(to_pcie_link_speed(lnksta)); pcie_link_speed_mbps() calls pcie_link_speed_to_mbps(), seems quite confusing to me. Perhaps renaming one to pcie_dev_speed_mbps() would help against the almost identical naming. In general, I don't like moving that code into a header file, did you check how large footprint the new function is (when it's not inlined)? Unrelated to this patch, it would be nice if LNKSTA register read would not be needed at all here but since cur_bus_speed is what it is currently, it's just wishful thinking. > } > EXPORT_SYMBOL(pcie_link_speed_mbps); > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 1b021579f26a..391a5cd388bd 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -333,6 +333,28 @@ void pci_bus_put(struct pci_bus *bus); > (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ > 0) > > +static inline int pcie_link_speed_to_mbps(enum pci_bus_speed speed) > +{ > + switch (speed) { > + case PCIE_SPEED_2_5GT: > + return 2500; > + case PCIE_SPEED_5_0GT: > + return 5000; > + case PCIE_SPEED_8_0GT: > + return 8000; > + case PCIE_SPEED_16_0GT: > + return 16000; > + case PCIE_SPEED_32_0GT: > + return 32000; > + case PCIE_SPEED_64_0GT: > + return 64000; > + default: > + break; > + } > + > + return -EINVAL; > +} -- i.