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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c4b3dc2sm1278206b3a.34.2026.04.09.21.48.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Apr 2026 21:48:23 -0700 (PDT) Message-ID: Date: Fri, 10 Apr 2026 12:48:17 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/8] clk: qcom: videocc: Add video clock controller driver for Eliza To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Konrad Dybcio References: <20260409-eliza_mm_cc_v2-v2-0-bc0c6dd77bc5@oss.qualcomm.com> <20260409-eliza_mm_cc_v2-v2-4-bc0c6dd77bc5@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20260409-eliza_mm_cc_v2-v2-4-bc0c6dd77bc5@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDA0MSBTYWx0ZWRfX1XJbE/S7gfYB +PGfk/Fgc40poaW343DQynaJ4h2DevbcRYYGen+lgYYCET7brDkF64QPbaqBi1zQ/P2tZTqrtPM Ki1uwjOXGz+WtHTiG6Y2ZzTCZ2foX90BYcjA8RbdiprOnjv5KatYuLPMOwAUqjKqAQ8iO7JaOMn t198FjdIPvZp82no7qe0PjTGHy3R18+DVG3bCjY4IJw+4sE4Mn405l6ZDUqgH/9Q1Jky6/6iA98 v9eJL5g0++lyVxPhuEV/s//VoLPv3mRZe4h/7hVZi4HcqzzL8guZw0dQWlzqJCvDZOayQj//ApB eoR2a5sFVwAzyjdTSpM9ZUOAFq11A0gYp9vIV3mvPG+yM4ghuy1Kjkt/1InqfmZFSKmJTiW3gOp GuRqYPSpPrXp7u/UPTKWitS5I+Y0zjX09S+Ik6DzBL18vsfzF5qgmKnjqC2jHhNG/oUb+44zcN2 NT8IaxQ9PKSYwZMEZDw== X-Authority-Analysis: v=2.4 cv=eOcjSnp1 c=1 sm=1 tr=0 ts=69d88119 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=JKCxmoqLevzGYRfko-YA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: DrRlCYsS9YDTwZGN75xmJ8vxnYO8RpN2 X-Proofpoint-ORIG-GUID: DrRlCYsS9YDTwZGN75xmJ8vxnYO8RpN2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_01,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100041 On 4/10/2026 2:10 AM, Taniya Das wrote: > Add support for the video clock controller for video clients to be able > to request for videocc clocks on Eliza platform. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/videocc-eliza.c | 403 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 413 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 22eb80be60ad3bde897f2c507ac9897951fbb8fe..4b0d40a38a6328fe9c41ebb15ae6821012223920 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -45,6 +45,15 @@ config CLK_ELIZA_TCSRCC > Support for the TCSR clock controller on Eliza devices. > Say Y if you want to use peripheral devices such as USB/PCIe/UFS. > > +config CLK_ELIZA_VIDEOCC > + tristate "Eliza Video Clock Controller" > + depends on ARM64 || COMPILE_TEST > + select CLK_GLYMUR_GCC Hi, My bot found a [BUG] here, please ignore it if it's a false positive issue. CLK_ELIZA_VIDEOCC selects CLK_GLYMUR_GCC instead of CLK_ELIZA_GCC - select CLK_GLYMUR_GCC pulls in gcc-glymur.c instead of gcc-eliza.c - On an Eliza system, gcc-glymur.c will never probe (no matching DTS node), so GCC_VIDEO_AHB_CLK from the Eliza GCC will never be available to videocc - The videocc driver's clocks = <&gcc GCC_VIDEO_AHB_CLK> will fail to resolve at runtime - The correct fix is select CLK_ELIZA_GCC, consistent with all other Eliza clock controllers Thanks, Jie > + help > + Support for the video clock controller on Eliza devices. > + Say Y if you want to support video devices and functionality such as > + video encode and decode. > + > config CLK_GLYMUR_DISPCC > tristate "Glymur Display Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index b818fd5af8bfb85a51ee90fdc3baa93af30dc39a..e7e239c5a0d088b2e78354bf421d871a4e4e6d9d 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o > obj-$(CONFIG_CLK_ELIZA_DISPCC) += dispcc-eliza.o > obj-$(CONFIG_CLK_ELIZA_GCC) += gcc-eliza.o > obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o > +obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o > obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o > obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o > diff --git a/drivers/clk/qcom/videocc-eliza.c b/drivers/clk/qcom/videocc-eliza.c > new file mode 100644 > index 0000000000000000000000000000000000000000..cb541cfec50c12761251a822e32094e763922cdb > --- /dev/null > +++ b/drivers/clk/qcom/videocc-eliza.c > @@ -0,0 +1,403 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "clk-regmap-divider.h" > +#include "clk-regmap-mux.h" > +#include "common.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + DT_BI_TCXO, > + DT_SLEEP_CLK, > + DT_AHB_CLK, > +}; > + > +enum { > + P_BI_TCXO, > + P_SLEEP_CLK, > + P_VIDEO_CC_PLL0_OUT_MAIN, > +}; > + > +static const struct pll_vco lucid_ole_vco[] = { > + { 249600000, 2300000000, 0 }, > +}; > + > +/* 576.0 MHz Configuration */ > +static const struct alpha_pll_config video_cc_pll0_config = { > + .l = 0x1e, > + .alpha = 0x0, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll video_cc_pll0 = { > + .offset = 0x0, > + .config = &video_cc_pll0_config, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "video_cc_pll0", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct parent_map video_cc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > +}; > + > +static const struct clk_parent_data video_cc_parent_data_0[] = { > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct parent_map video_cc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, > +}; > + > +static const struct clk_parent_data video_cc_parent_data_1[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &video_cc_pll0.clkr.hw }, > +}; > + > +static const struct parent_map video_cc_parent_map_2[] = { > + { P_SLEEP_CLK, 0 }, > +}; > + > +static const struct clk_parent_data video_cc_parent_data_2[] = { > + { .index = DT_SLEEP_CLK }, > +}; > + > +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 video_cc_ahb_clk_src = { > + .cmd_rcgr = 0x8018, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = video_cc_parent_map_0, > + .freq_tbl = ftbl_video_cc_ahb_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "video_cc_ahb_clk_src", > + .parent_data = video_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { > + F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(633000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(1113000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 video_cc_mvs0_clk_src = { > + .cmd_rcgr = 0x8000, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = video_cc_parent_map_1, > + .freq_tbl = ftbl_video_cc_mvs0_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0_clk_src", > + .parent_data = video_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { > + F(32000, P_SLEEP_CLK, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 video_cc_sleep_clk_src = { > + .cmd_rcgr = 0x8110, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = video_cc_parent_map_2, > + .freq_tbl = ftbl_video_cc_sleep_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "video_cc_sleep_clk_src", > + .parent_data = video_cc_parent_data_2, > + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 video_cc_xo_clk_src = { > + .cmd_rcgr = 0x80f4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = video_cc_parent_map_0, > + .freq_tbl = ftbl_video_cc_ahb_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "video_cc_xo_clk_src", > + .parent_data = video_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_regmap_div video_cc_mvs0_div_clk_src = { > + .reg = 0x80ac, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0_div_clk_src", > + .parent_hws = (const struct clk_hw*[]) { > + &video_cc_mvs0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { > + .reg = 0x8058, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0c_div2_div_clk_src", > + .parent_hws = (const struct clk_hw*[]) { > + &video_cc_mvs0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_branch video_cc_mvs0_clk = { > + .halt_reg = 0x80a0, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x80a0, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x80a0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &video_cc_mvs0_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch video_cc_mvs0_shift_clk = { > + .halt_reg = 0x8144, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x8144, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x8144, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0_shift_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &video_cc_xo_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch video_cc_mvs0c_clk = { > + .halt_reg = 0x804c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x804c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0c_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch video_cc_mvs0c_shift_clk = { > + .halt_reg = 0x8148, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x8148, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x8148, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "video_cc_mvs0c_shift_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &video_cc_xo_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct gdsc video_cc_mvs0c_gdsc = { > + .gdscr = 0x8034, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x6, > + .pd = { > + .name = "video_cc_mvs0c_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc video_cc_mvs0_gdsc = { > + .gdscr = 0x808c, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x6, > + .pd = { > + .name = "video_cc_mvs0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .parent = &video_cc_mvs0c_gdsc.pd, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, > +}; > + > +static struct clk_regmap *video_cc_eliza_clocks[] = { > + [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr, > + [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, > + [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, > + [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, > + [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, > + [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, > + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, > + [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, > + [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, > + [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, > + [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, > +}; > + > +static struct gdsc *video_cc_eliza_gdscs[] = { > + [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, > + [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, > +}; > + > +static const struct qcom_reset_map video_cc_eliza_resets[] = { > + [VIDEO_CC_INTERFACE_BCR] = { 0x80d8 }, > + [VIDEO_CC_MVS0_CLK_ARES] = { 0x80a0, 2 }, > + [VIDEO_CC_MVS0_BCR] = { 0x8088 }, > + [VIDEO_CC_MVS0C_CLK_ARES] = { 0x804c, 2 }, > + [VIDEO_CC_MVS0C_BCR] = { 0x8030 }, > + [VIDEO_CC_XO_CLK_ARES] = { 0x810c, 2 }, > +}; > + > +static struct clk_alpha_pll *video_cc_eliza_plls[] = { > + &video_cc_pll0, > +}; > + > +static u32 video_cc_eliza_critical_cbcrs[] = { > + 0x80dc, /* VIDEO_CC_AHB_CLK */ > + 0x8128, /* VIDEO_CC_SLEEP_CLK */ > + 0x810c, /* VIDEO_CC_XO_CLK */ > +}; > + > +static const struct regmap_config video_cc_eliza_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x9f50, > + .fast_io = true, > +}; > + > +static struct qcom_cc_driver_data video_cc_eliza_driver_data = { > + .alpha_plls = video_cc_eliza_plls, > + .num_alpha_plls = ARRAY_SIZE(video_cc_eliza_plls), > + .clk_cbcrs = video_cc_eliza_critical_cbcrs, > + .num_clk_cbcrs = ARRAY_SIZE(video_cc_eliza_critical_cbcrs), > +}; > + > +static const struct qcom_cc_desc video_cc_eliza_desc = { > + .config = &video_cc_eliza_regmap_config, > + .clks = video_cc_eliza_clocks, > + .num_clks = ARRAY_SIZE(video_cc_eliza_clocks), > + .resets = video_cc_eliza_resets, > + .num_resets = ARRAY_SIZE(video_cc_eliza_resets), > + .gdscs = video_cc_eliza_gdscs, > + .num_gdscs = ARRAY_SIZE(video_cc_eliza_gdscs), > + .driver_data = &video_cc_eliza_driver_data, > +}; > + > +static const struct of_device_id video_cc_eliza_match_table[] = { > + { .compatible = "qcom,eliza-videocc" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, video_cc_eliza_match_table); > + > +static int video_cc_eliza_probe(struct platform_device *pdev) > +{ > + return qcom_cc_probe(pdev, &video_cc_eliza_desc); > +} > + > +static struct platform_driver video_cc_eliza_driver = { > + .probe = video_cc_eliza_probe, > + .driver = { > + .name = "videocc-eliza", > + .of_match_table = video_cc_eliza_match_table, > + }, > +}; > + > +module_platform_driver(video_cc_eliza_driver); > + > +MODULE_DESCRIPTION("QTI VIDEOCC Eliza Driver"); > +MODULE_LICENSE("GPL"); >