From mboxrd@z Thu Jan 1 00:00:00 1970 From: Srinivas Kandagatla Subject: Re: [PATCH] irqchip/gic-v3: Support MSIs via aliases and distributor Date: Tue, 28 Nov 2017 07:16:29 +0000 Message-ID: References: <20171127102408.6631-1-sboyd@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20171127102408.6631-1-sboyd@codeaurora.org> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Stephen Boyd , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Hi Stephen, Thanks for the patch. On 27/11/17 10:24, Stephen Boyd wrote: > Some GIC configurations don't have an accessible ITS, but they > want to support MSIs through the distributor's SETSPI registers > or through the IMPLEMENTATION DEFINED message-based interrupt > request register region. This mode of operation is similar to the > v2m support on gic-400, but we don't necessarily know what > particular SPIs are supported as MSIs so we need some help from > firmware to know what to do. > > Introduce an "arm,spi-ranges" property for this, similar to the > "marvell,spi-ranges" property, that indicates the base and size > of each MSI range. This property applies equally to the > distributor and alias registers. In either case, we detect this > mode of operation by looking for a node with the "msi-controller" > property and then probe the v2m frame code on top of it. Assume > these nodes will have the "arm,spi-ranges" property in them so > that the v2m code works mostly unmodified. > > Cc: > Cc: Srinivas Kandagatla > Cc: Marc Zyngier > Signed-off-by: Stephen Boyd Tested it on DB820c board. Tested-by: Srinivas Kandagatla