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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id s27-20020a056512203b00b004afac783b5esm790585lfs.238.2022.12.14.04.51.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Dec 2022 04:51:31 -0800 (PST) Message-ID: Date: Wed, 14 Dec 2022 13:51:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH 3/4] arm64: dts: qcom: sa8540p-ride: add qup1_i2c15 and qup2_i2c18 nodes To: Brian Masney , andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com, quic_shazhuss@quicinc.com References: <20221212182314.1902632-1-bmasney@redhat.com> <20221212182314.1902632-4-bmasney@redhat.com> Content-Language: en-US From: Krzysztof Kozlowski In-Reply-To: <20221212182314.1902632-4-bmasney@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 12/12/2022 19:23, Brian Masney wrote: > Add the necessary nodes in order to get qup1_i2c15 and qup2_i2c18 > functioning on the automotive board and exposed to userspace. > > This work was derived from various patches that Qualcomm delivered > to Red Hat in a downstream kernel. This change was validated by using > i2c-tools 4.3.3 on CentOS Stream 9: > > [root@localhost ~]# i2cdetect -l > i2c-15 i2c Geni-I2C I2C adapter > i2c-18 i2c Geni-I2C I2C adapter > > [root@localhost ~]# i2cdetect -a -y 15 > Warning: Can't use SMBus Quick Write command, will skip some addresses > 0 1 2 3 4 5 6 7 8 9 a b c d e f > 00: > 10: > 20: > 30: -- -- -- -- -- -- -- -- > 40: > 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- > 60: > 70: > > Bus 18 has the same output. I validated that we get the same output on > the downstream kernel. > > Signed-off-by: Brian Masney > --- > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 46 +++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > index d70859803fbd..6dc3f3ff8ece 100644 > --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > @@ -17,6 +17,8 @@ / { > compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; > > aliases { > + i2c15 = &qup1_i2c15; > + i2c18 = &qup2_i2c18; > serial0 = &qup2_uart17; > }; > > @@ -188,10 +190,28 @@ &pcie3a_phy { > status = "okay"; > }; > > +&qup1 { > + status = "okay"; > +}; > + > +&qup1_i2c15 { > + pinctrl-names = "default"; > + pinctrl-0 = <&qup1_i2c15_default>; > + > + status = "okay"; > +}; > + > &qup2 { > status = "okay"; > }; > > +&qup2_i2c18 { > + pinctrl-names = "default"; > + pinctrl-0 = <&qup2_i2c18_default>; > + > + status = "okay"; > +}; > + > &qup2_uart17 { > compatible = "qcom,geni-debug-uart"; > status = "okay"; > @@ -313,4 +333,30 @@ wake-pins { > bias-pull-up; > }; > }; > + > + qup1_i2c15_default: qup1-i2c15-state { > + mux-pins { > + pins = "gpio36", "gpio37"; > + function = "qup15"; > + }; > + > + config-pins { > + pins = "gpio36", "gpio37"; > + drive-strength = <0x02>; Except the problem pointed out by Konrad (we do not have separate mux and config pins anymore), this is not a hex, it's mA. Best regards, Krzysztof