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Thu, 14 Sep 2023 00:58:34 -0700 (PDT) Received: from [192.168.1.20] ([178.197.214.188]) by smtp.gmail.com with ESMTPSA id k8-20020a5d4288000000b00317a29af4b2sm1007983wrq.68.2023.09.14.00.58.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 00:58:33 -0700 (PDT) Message-ID: Date: Thu, 14 Sep 2023 09:58:31 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH v7 4/4] clk: qcom: add clock controller driver for qca8386/qca8084 Content-Language: en-US To: Jie Luo , andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, p.zabel@pengutronix.de Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com References: <20230914054639.13075-1-quic_luoj@quicinc.com> <20230914054639.13075-5-quic_luoj@quicinc.com> <357805c5-bedb-8972-bcf1-fabaaaf90ad9@linaro.org> <1a1922ec-a8ae-4a42-d8a9-921450592213@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <1a1922ec-a8ae-4a42-d8a9-921450592213@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 14/09/2023 09:52, Jie Luo wrote: > > > On 9/14/2023 2:15 PM, Krzysztof Kozlowski wrote: >> On 14/09/2023 07:46, Luo Jie wrote: >>> The clock controller driver of qca8386/qca8084 is registered >>> as the MDIO device, the hardware register is accessed by MDIO bus >>> that is normally used to access general PHY device, which is >>> different from the current existed qcom clock controller drivers >>> using ioremap to access hardware clock registers. >>> >>> MDIO bus is common utilized by both qca8386/qca8084 and other >>> PHY devices, so the mutex lock mdio_bus->mdio_lock should be >>> used instead of using the mutex lock of remap. >>> >>> To access the hardware clock registers of qca8386/qca8084, there >>> is special MDIO frame sequence(three MDIO read/write operations) >>> need to be sent to device. >>> >>> Signed-off-by: Luo Jie >>> --- >>> drivers/clk/qcom/Kconfig | 9 + >>> drivers/clk/qcom/Makefile | 1 + >>> drivers/clk/qcom/nsscc-qca8k.c | 2178 ++++++++++++++++++++++++++++++++ >>> 3 files changed, 2188 insertions(+) >>> create mode 100644 drivers/clk/qcom/nsscc-qca8k.c >>> >>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >>> index 865db5202e4c..c95ada6a1385 100644 >>> --- a/drivers/clk/qcom/Kconfig >>> +++ b/drivers/clk/qcom/Kconfig >>> @@ -203,6 +203,15 @@ config IPQ_GCC_9574 >>> i2c, USB, SD/eMMC, etc. Select this for the root clock >>> of ipq9574. >>> >>> +config IPQ_NSSCC_QCA8K >>> + tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" >>> + depends on MDIO_BUS || COMPILE_TEST >> >> This is SoC is for both ARM and ARM64 worlds? >> > Thanks Krzysztof for the comments. > This chip is independent of the ARCH, which just depends on the MDIO > bus, both mips and arm are supported. There is no ARCH_QCOM on MIPS, so it's limited to ARM. Then add restriction to ARM || COMPILE_TEST. Best regards, Krzysztof