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Mon, 25 Sep 2023 20:15:34 -0700 (PDT) Message-ID: Subject: Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties From: Icenowy Zheng To: Conor Dooley Cc: linux-riscv@lists.infradead.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Date: Tue, 26 Sep 2023 11:15:27 +0800 In-Reply-To: <20230925-semantic-euphemism-f0c7e85ac317@spud> References: <20230922081351.30239-2-conor@kernel.org> <20230922081351.30239-8-conor@kernel.org> <20230925-semantic-euphemism-f0c7e85ac317@spud> Organization: Anthon Open-Source Community Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-0.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net =E5=9C=A8 2023-09-25=E6=98=9F=E6=9C=9F=E4=B8=80=E7=9A=84 16:59 +0100=EF=BC= =8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A > On Sun, Sep 24, 2023 at 07:22:30AM +0800, Icenowy Zheng wrote: > > =E5=9C=A8 2023-09-22=E6=98=9F=E6=9C=9F=E4=BA=94=E7=9A=84 09:13 +0100=EF= =BC=8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A > > > From: Conor Dooley > > >=20 > > > Convert the th1520 devicetrees to use the new properties > > > "riscv,isa-base" & "riscv,isa-extensions". > > > For compatibility with other projects, "riscv,isa" remains. > > >=20 > > > Signed-off-by: Conor Dooley > > > --- > > > =C2=A0arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ > > > =C2=A01 file changed, 12 insertions(+) > > >=20 > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi > > > b/arch/riscv/boot/dts/thead/th1520.dtsi > > > index ce708183b6f6..723f65487246 100644 > > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > > @@ -20,6 +20,9 @@ c910_0: cpu@0 { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= compatible =3D "thead,c910", "riscv"; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= device_type =3D "cpu"; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= riscv,isa =3D "rv64imafdc"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0ris= cv,isa-base =3D "rv64i"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0ris= cv,isa-extensions =3D "i", "m", "a", > > > "f", > > > "d", "c", "zicntr", "zicsr", > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", > > > "zihpm"; > >=20 > > Zfh is supported by T-Head C9xx with float too. >=20 > You say xx, so just to be sure: Is it always supported, or only with > some config for the IP (I wanna know if I need to look out for it > while > reviewing other SoCs etc)? I think it's grouped with FD. > Also, do you have a link to the documentation for it? English is the > only relevant language I speak, so if the doc is in Chinese, I'll > need > some help! Sorry, but T-Head's official document [1] is only in Chinese. In addition, in this document half-float is listed as a "T-Head extension", but the encoding matches Zfh. See 15.6 Appendix B-6 Half Float (15.6 =E9=99=84=E5=BD=95 B-6 =E6=B5=AE=E7=82=B9=E5=8D=8A=E7=B2=BE=E5= =BA=A6=E6=8C=87=E4=BB=A4=E6=9C=AF=E8=AF=AD) . [1] https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C91= 0%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf >=20 > > In addition, should X extensions get listed here? >=20 > Yes, but someone who cares about documenting these extensions should > do > it ;) Well at least a bunch of Xthead's are now documented. Maybe they will get appended after this patchset get introduced. By the way, how to deal with the draft V of C9xx? >=20 > Thanks, > Conor.