From: Dan Carpenter <dan.carpenter@linaro.org>
To: Chester Lin <chester62515@gmail.com>
Cc: Matthias Brugger <mbrugger@suse.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
NXP S32 Linux Team <s32@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linaro-s32@linaro.org
Subject: [PATCH 4/4] dts: s32g: Add GPR syscon region
Date: Mon, 1 Dec 2025 16:08:33 +0300 [thread overview]
Message-ID: <c8302f53fcbb5cb5afe42cdb15aba7e2e6ed7338.1764592300.git.dan.carpenter@linaro.org> (raw)
In-Reply-To: <cover.1764592300.git.dan.carpenter@linaro.org>
Add the GPR syscon region for the s32 chipset.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..3c9472f6c174 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -325,6 +325,13 @@ usdhc0-200mhz-grp4 {
};
};
+ gpr: syscon@4007c000 {
+ compatible = "nxp,s32-gpr", "syscon";
+ reg = <0x4007c000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
ocotp: nvmem@400a4000 {
compatible = "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
@@ -731,6 +738,7 @@ gmac0: ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
+ phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index eff7673e7f34..0ceca3caf133 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -383,6 +383,13 @@ usdhc0-200mhz-grp4 {
};
};
+ gpr: syscon@4007c000 {
+ compatible = "nxp,s32-gpr", "syscon";
+ reg = <0x4007c000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
ocotp: nvmem@400a4000 {
compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
@@ -808,6 +815,7 @@ gmac0: ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
+ phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.51.0
next prev parent reply other threads:[~2025-12-01 13:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-01 13:08 [PATCH 0/4] s32g: Use a syscon for GPR Dan Carpenter
2025-12-01 13:08 ` [PATCH 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs Dan Carpenter
2025-12-01 17:30 ` Krzysztof Kozlowski
2025-12-01 13:08 ` [PATCH 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
2025-12-01 17:33 ` Krzysztof Kozlowski
2025-12-15 10:59 ` Dan Carpenter
2025-12-15 11:03 ` Dan Carpenter
2025-12-01 13:08 ` Dan Carpenter [this message]
2025-12-01 16:42 ` [PATCH 4/4] dts: s32g: Add GPR syscon region Frank Li
2025-12-01 16:55 ` Russell King (Oracle)
2025-12-01 14:31 ` [PATCH 0/4] s32g: Use a syscon for GPR Dan Carpenter
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