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Thu, 23 Jul 2026 21:46:39 -0700 (PDT) X-Received: by 2002:a05:6300:2204:b0:3bf:a38b:e8ca with SMTP id adf61e73a8af0-3c44b211035mr6789544637.59.1784868398747; Thu, 23 Jul 2026 21:46:38 -0700 (PDT) Received: from [10.218.31.237] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147df09ac0sm22951882eec.16.2026.07.23.21.46.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Jul 2026 21:46:38 -0700 (PDT) Message-ID: Date: Fri, 24 Jul 2026 10:16:31 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] net: wwan: qcom_bam_dmux: Alloc RX buffers as a single coherent block To: Stephan Gerhold Cc: Stephan Gerhold , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Sergey Ryazanov , Johannes Berg , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, chris.lew@oss.qualcomm.com, Deepak Kumar Singh References: <20260714-qcom-bam-dmux-vmid-ext-v1-0-3f29da7cca76@oss.qualcomm.com> <20260714-qcom-bam-dmux-vmid-ext-v1-2-3f29da7cca76@oss.qualcomm.com> Content-Language: en-US From: Vishnu Santhosh In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA0MCBTYWx0ZWRfX2vIqHohoyyH3 kXFRMBHAD7ONPUZxZb3rJgSABC6Xlete+1Q4EUb09f2SjNARwY36ISsUEgqyfZbyq5MlDHXFwFP 2EXDgenZleZ5bcoEdRAyb4Q7MVjkRtdYb0FceR4CxKGCMdv4rBXRx0zIEVbr4XtK6FZI2/s+NbN 5unK8vYpYT3/yACmWvLbLWrqM0tag/Jm29/rjtcCKe/bti+tR+Vwl2iOMQ8eiy1JWiUsD14YaC9 9PnZ0LK/7mgRVDaBy1yax/cC4Y/TQz2p0ICjOFHx2qbeMKzQXM43P2poG9Dvg8FuIs5tjWVcD5M 1KIgpLZ1mwAEYmaBnbDDCoTDoYF1rCr7C63HzRc3r3P8pTZCZBZKBS9Q1ZmX6RQtYJrFIrFhZ9X //5BRwmIxV1hQYKJd+mO0dUS5UFYxP1lqXDEqwFH0MNTds17CN9OGcL0b9tpVeHBBxxMQYcjDHl tjyqtGdVvFWAjkBR/bg== X-Authority-Analysis: v=2.4 cv=RJeD2Yi+ c=1 sm=1 tr=0 ts=6a62ee30 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=2eDN7aXksB4whfXZn5AA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: _9d3Y1Z6smGD1Kl7z3U4wJW-cMhAVYNk X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA0MCBTYWx0ZWRfX8hdepnhYY+/i Uty/hsZowMOW2UdJgvX+vjnD9oZvctdeaScH7ZK0cm1JZ5yRmIganXjL6Tmr6y8EPcgt9YwGRY1 RokIiP9oQ8rVtobCvhqqoV9KBtc/N1Q= X-Proofpoint-GUID: _9d3Y1Z6smGD1Kl7z3U4wJW-cMhAVYNk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-23_07,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240040 On 14-07-2026 01:05 pm, Stephan Gerhold wrote: > On Tue, Jul 14, 2026 at 11:02:32AM +0530, Vishnu Santhosh wrote: >> On Qualcomm SoCs where the modem (e.g. the mDSP on Shikra, VMID 43 / >> NAV) is the AXI master for BAM-DMUX RX transfers and the XPU enforces >> per-region access control, each individually DMA-mapped RX buffer >> requires its own XPU resource group (RG). With ~16 RGs available, the >> 32 per-buffer dma_map_single() calls exhaust the table and the first >> inbound transfer faults with an XPU violation. >> >> BAM-DMUX is a singleton (exactly one instance per SoC), so the >> destination VMID does not need to be a DT property; it is looked up >> from the compatible string's match data instead. Add struct >> bam_dmux_data with a single vmid field, and a shikra_data instance >> hardcoding QCOM_SCM_VMID_NAV for qcom,shikra-bam-dmux. >> >> When match data is present, allocate all BAM_DMUX_NUM_SKB RX buffers as >> a single contiguous dma_alloc_coherent() block and SCM-assign that >> block to HLOS plus the VMID once at probe. This reduces RG consumption >> from 32 to 1. The block is never reclaimed across a modem power cycle >> (bam_dmux_power_off() does not touch it), so the probe-time assignment >> covers every subsequent restart without re-assigning or reclaiming. It >> is reclaimed to HLOS only once, at remove or on a probe error, and if >> that reclaim fails it is leaked rather than returned to the page >> allocator. >> >> Each rx_skbs[] slot is pre-assigned its virtual and DMA address from >> the block, so no per-buffer mapping is needed at power-on. Because the >> coherent block is not page-backed, received payload is copied into a >> regular netdev skb before handoff to the network stack; this is an >> unavoidable extra copy on the XPU-enforced RX path. >> >> Platforms without match data are unaffected: rx_virt stays NULL, no >> coherent memory is allocated, and the per-buffer dma_map_single() path >> is unchanged. >> >> Co-developed-by: Deepak Kumar Singh >> Signed-off-by: Deepak Kumar Singh >> Signed-off-by: Vishnu Santhosh > So how do you handle TX buffers? Right now, they are just passed on from > the net subsystem. There can be up to 32 TX buffers in progress as well. > > Overall, I have mixed feelings about this patch. It looks reasonably > simple, but fundamentally I don't understand why we need to go back to > the old days of implementing protection using a highly limited MPU (in > your case: the xPU). > > Why does the setup of BAM-DMUX differ e.g. from the setup for the crypto > engine? Crypto is also using bam-dma, but it avoids this inflexibility > by making use of the &apps_smmu. Is BAM-DMUX not covered by the SMMU? Or > did you just decide to bypass the SMMU in this case? (If so: Why?) I checked with secure systems team on this. Crypto BAM is behind apps_smmu, so protection is enforced through the SMMU's Stage-2 page tables. A2 BAM (used by BAM-DMUX) is present in secure domain and does not support Stage-2 translation on this SoC, and there is no IOMMU domain that can be attached to it. The only protection mechanism available is the xPU. Thanks, Vishnu > > If you had BAM-DMUX mapped using the SMMU you would get all of this for > free. No changes would be needed in the BAM-DMUX driver ... > > Thanks, > Stephan