* [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings
@ 2022-03-25 15:40 Jae Hyun Yoo
2022-03-25 15:40 ` [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi Jae Hyun Yoo
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Jae Hyun Yoo @ 2022-03-25 15:40 UTC (permalink / raw)
To: Rob Herring, Joel Stanley, Andrew Jeffery, Andrew Lunn
Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel,
linux-aspeed, Jae Hyun Yoo
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I’m sending this patch series to fix current issues in AST2600 pinmux
settings while enabling quad mode SPI support.
FWSPI18 pins are basically 1.8v logic pins that are different from the
dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t
be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to
make it able to enable quad mode on SPI1 and SPI2 interfaces.
With this series, quad mode pinmux can be set like below.
FW SPI:
&fmc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fwqspi_default>;
}
SPI1:
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
}
SPI2:
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2_default>;
}
Please review.
Thanks,
Jae
Changes in v2:
* Rebased it on the latest.
Jae Hyun Yoo (3):
ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi
pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group
Johnny Huang (2):
pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi
arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 10 +++++-----
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 17 ++++++++---------
2 files changed, 13 insertions(+), 14 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi 2022-03-25 15:40 [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo @ 2022-03-25 15:40 ` Jae Hyun Yoo 2022-03-28 3:09 ` Andrew Jeffery 2022-03-25 15:40 ` [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl Jae Hyun Yoo ` (3 subsequent siblings) 4 siblings, 1 reply; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-25 15:40 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Jae Hyun Yoo FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl dtsi. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Fixes: 2f6edb6bcb2f ("ARM: dts: aspeed: Fix AST2600 quad spi group") --- Changes in v2: * Rebased it on the latest. * Updated 'Fixes' while rebasing it on the latest. Note: * Removing 'pinctrl_fwqspid_default' doesn't break any existing DT since it has not been used in any DTs. arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index e4775bbceecc..06d60a8540e9 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -117,11 +117,6 @@ pinctrl_fwspid_default: fwspid_default { groups = "FWSPID"; }; - pinctrl_fwqspid_default: fwqspid_default { - function = "FWSPID"; - groups = "FWQSPID"; - }; - pinctrl_fwspiwp_default: fwspiwp_default { function = "FWSPIWP"; groups = "FWSPIWP"; -- 2.25.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi 2022-03-25 15:40 ` [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi Jae Hyun Yoo @ 2022-03-28 3:09 ` Andrew Jeffery 2022-03-28 14:26 ` Jae Hyun Yoo 0 siblings, 1 reply; 18+ messages in thread From: Andrew Jeffery @ 2022-03-28 3:09 UTC (permalink / raw) To: Jae Hyun Yoo, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: > FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove > FWQSPID group in pinctrl dtsi. These pins must be used with the > FWSPI pins that are dedicated for boot SPI interface which provides > same 3.3v logic level. > > Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> > Fixes: 2f6edb6bcb2f ("ARM: dts: aspeed: Fix AST2600 quad spi group") > --- > Changes in v2: > * Rebased it on the latest. > * Updated 'Fixes' while rebasing it on the latest. > > Note: > * Removing 'pinctrl_fwqspid_default' doesn't break any existing DT since > it has not been used in any DTs. Can you please send a patch to the bindings to drop the broken function/group given they never worked and no-one could be using them? Other than that, Reviewed-by: Andrew Jeffery <andrew@aj.id.au> ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi 2022-03-28 3:09 ` Andrew Jeffery @ 2022-03-28 14:26 ` Jae Hyun Yoo 0 siblings, 0 replies; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-28 14:26 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On 3/27/2022 8:09 PM, Andrew Jeffery wrote: > > > On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >> FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove >> FWQSPID group in pinctrl dtsi. These pins must be used with the >> FWSPI pins that are dedicated for boot SPI interface which provides >> same 3.3v logic level. >> >> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >> Fixes: 2f6edb6bcb2f ("ARM: dts: aspeed: Fix AST2600 quad spi group") >> --- >> Changes in v2: >> * Rebased it on the latest. >> * Updated 'Fixes' while rebasing it on the latest. >> >> Note: >> * Removing 'pinctrl_fwqspid_default' doesn't break any existing DT since >> it has not been used in any DTs. > > Can you please send a patch to the bindings to drop the broken > function/group given they never worked and no-one could be using them? Sure, I'll send a bindings patch too in v3. Thanks for your review! -Jae > Other than that, > > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl 2022-03-25 15:40 [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi Jae Hyun Yoo @ 2022-03-25 15:40 ` Jae Hyun Yoo 2022-03-28 3:18 ` Andrew Jeffery 2022-03-25 15:40 ` [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Jae Hyun Yoo ` (2 subsequent siblings) 4 siblings, 1 reply; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-25 15:40 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Jae Hyun Yoo FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") --- Changes in v2: * None. drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index a3fa03bcd9a3..54064714d73f 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1236,18 +1236,12 @@ FUNC_GROUP_DECL(SALT8, AA12); FUNC_GROUP_DECL(WDTRST4, AA12); #define AE12 196 -SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, - SIG_DESC_SET(SCU438, 4)); SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), - SIG_EXPR_LIST_PTR(AE12, GPIOY4)); +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); #define AF12 197 -SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, - SIG_DESC_SET(SCU438, 5)); SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), - SIG_EXPR_LIST_PTR(AF12, GPIOY5)); +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); #define AC12 198 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); @@ -1520,9 +1514,8 @@ SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3)); PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); -GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4); -FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); +FUNC_DECL_1(FWSPID, FWSPID); FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); /* @@ -1918,7 +1911,6 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(FSI2), ASPEED_PINCTRL_GROUP(FWSPIABR), ASPEED_PINCTRL_GROUP(FWSPID), - ASPEED_PINCTRL_GROUP(FWQSPID), ASPEED_PINCTRL_GROUP(FWSPIWP), ASPEED_PINCTRL_GROUP(GPIT0), ASPEED_PINCTRL_GROUP(GPIT1), -- 2.25.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl 2022-03-25 15:40 ` [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl Jae Hyun Yoo @ 2022-03-28 3:18 ` Andrew Jeffery 2022-03-28 14:41 ` Jae Hyun Yoo 0 siblings, 1 reply; 18+ messages in thread From: Andrew Jeffery @ 2022-03-28 3:18 UTC (permalink / raw) To: Jae Hyun Yoo, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: > FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove > FWQSPID group in pinctrl. These pins must be used with the FWSPI > pins that are dedicated for boot SPI interface which provides > same 3.3v logic level. > > Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> > Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") > --- > Changes in v2: > * None. > > drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 14 +++----------- > 1 file changed, 3 insertions(+), 11 deletions(-) > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > index a3fa03bcd9a3..54064714d73f 100644 > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > @@ -1236,18 +1236,12 @@ FUNC_GROUP_DECL(SALT8, AA12); > FUNC_GROUP_DECL(WDTRST4, AA12); > > #define AE12 196 > -SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, > - SIG_DESC_SET(SCU438, 4)); > SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); > -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), > - SIG_EXPR_LIST_PTR(AE12, GPIOY4)); > +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); > > #define AF12 197 > -SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, > - SIG_DESC_SET(SCU438, 5)); > SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); > -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), > - SIG_EXPR_LIST_PTR(AF12, GPIOY5)); > +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); > > #define AC12 198 > SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); > @@ -1520,9 +1514,8 @@ SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, > EMMC, SIG_DESC_SET(SCU404, 3)); > PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); > > GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); > -GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); > GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, > Y4); > -FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); > +FUNC_DECL_1(FWSPID, FWSPID); Really this is the FWSPI18 group now? The FWSPID name never made sense. I'm not sure what I was thinking. Actually, I think it's worth squashing this with 3/5 so it's a proper fix rather than separate remove/add? > FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); > FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); > /* > @@ -1918,7 +1911,6 @@ static const struct aspeed_pin_group > aspeed_g6_groups[] = { > ASPEED_PINCTRL_GROUP(FSI2), > ASPEED_PINCTRL_GROUP(FWSPIABR), > ASPEED_PINCTRL_GROUP(FWSPID), > - ASPEED_PINCTRL_GROUP(FWQSPID), We should also remove the function (not just the group). Andrew > ASPEED_PINCTRL_GROUP(FWSPIWP), > ASPEED_PINCTRL_GROUP(GPIT0), > ASPEED_PINCTRL_GROUP(GPIT1), > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl 2022-03-28 3:18 ` Andrew Jeffery @ 2022-03-28 14:41 ` Jae Hyun Yoo 2022-03-28 23:01 ` Andrew Jeffery 0 siblings, 1 reply; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-28 14:41 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On 3/27/2022 8:18 PM, Andrew Jeffery wrote: > > > On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >> FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove >> FWQSPID group in pinctrl. These pins must be used with the FWSPI >> pins that are dedicated for boot SPI interface which provides >> same 3.3v logic level. >> >> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") >> --- >> Changes in v2: >> * None. >> >> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 14 +++----------- >> 1 file changed, 3 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> index a3fa03bcd9a3..54064714d73f 100644 >> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> @@ -1236,18 +1236,12 @@ FUNC_GROUP_DECL(SALT8, AA12); >> FUNC_GROUP_DECL(WDTRST4, AA12); >> >> #define AE12 196 >> -SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, >> - SIG_DESC_SET(SCU438, 4)); >> SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); >> -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), >> - SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >> +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >> >> #define AF12 197 >> -SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, >> - SIG_DESC_SET(SCU438, 5)); >> SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); >> -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), >> - SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >> +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >> >> #define AC12 198 >> SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); >> @@ -1520,9 +1514,8 @@ SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, >> EMMC, SIG_DESC_SET(SCU404, 3)); >> PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); >> >> GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); >> -GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); >> GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, >> Y4); >> -FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); >> +FUNC_DECL_1(FWSPID, FWSPID); > > Really this is the FWSPI18 group now? The FWSPID name never made sense. > I'm not sure what I was thinking. Yes, it's now the FWSPI18 which is described as 'debug SPI' in the datasheet. Corresponding SCU500[3] bit is also described as that 'the bit is for verification and testing only'. Probably, you was thinking 'D' as in 'Debug' for the FWSPID naming. > Actually, I think it's worth squashing this with 3/5 so it's a proper > fix rather than separate remove/add? Two reasons I separated them. 1. Author is different. 2. 2/5 is a bug fix and 3/5 introduces a new pinmux. >> FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); >> FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); >> /* >> @@ -1918,7 +1911,6 @@ static const struct aspeed_pin_group >> aspeed_g6_groups[] = { >> ASPEED_PINCTRL_GROUP(FSI2), >> ASPEED_PINCTRL_GROUP(FWSPIABR), >> ASPEED_PINCTRL_GROUP(FWSPID), >> - ASPEED_PINCTRL_GROUP(FWQSPID), > > We should also remove the function (not just the group). Still worth to keep FWSPID to support SCU500[3] - Boot from debug SPI. FWSPID would work on single and dual data mode only. Thanks, Jae > > Andrew > >> ASPEED_PINCTRL_GROUP(FWSPIWP), >> ASPEED_PINCTRL_GROUP(GPIT0), >> ASPEED_PINCTRL_GROUP(GPIT1), >> -- >> 2.25.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl 2022-03-28 14:41 ` Jae Hyun Yoo @ 2022-03-28 23:01 ` Andrew Jeffery 2022-03-28 23:12 ` Jae Hyun Yoo 0 siblings, 1 reply; 18+ messages in thread From: Andrew Jeffery @ 2022-03-28 23:01 UTC (permalink / raw) To: Jae Hyun Yoo, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On Tue, 29 Mar 2022, at 01:11, Jae Hyun Yoo wrote: > On 3/27/2022 8:18 PM, Andrew Jeffery wrote: >> >> >> On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >>> FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove >>> FWQSPID group in pinctrl. These pins must be used with the FWSPI >>> pins that are dedicated for boot SPI interface which provides >>> same 3.3v logic level. >>> >>> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >>> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") >>> --- >>> Changes in v2: >>> * None. >>> >>> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 14 +++----------- >>> 1 file changed, 3 insertions(+), 11 deletions(-) >>> >>> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>> b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>> index a3fa03bcd9a3..54064714d73f 100644 >>> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>> @@ -1236,18 +1236,12 @@ FUNC_GROUP_DECL(SALT8, AA12); >>> FUNC_GROUP_DECL(WDTRST4, AA12); >>> >>> #define AE12 196 >>> -SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, >>> - SIG_DESC_SET(SCU438, 4)); >>> SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); >>> -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), >>> - SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >>> +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >>> >>> #define AF12 197 >>> -SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, >>> - SIG_DESC_SET(SCU438, 5)); >>> SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); >>> -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), >>> - SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >>> +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >>> >>> #define AC12 198 >>> SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); >>> @@ -1520,9 +1514,8 @@ SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, >>> EMMC, SIG_DESC_SET(SCU404, 3)); >>> PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); >>> >>> GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); >>> -GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); >>> GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, >>> Y4); >>> -FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); >>> +FUNC_DECL_1(FWSPID, FWSPID); >> >> Really this is the FWSPI18 group now? The FWSPID name never made sense. >> I'm not sure what I was thinking. > > Yes, it's now the FWSPI18 which is described as 'debug SPI' in the > datasheet. Corresponding SCU500[3] bit is also described as that 'the > bit is for verification and testing only'. Probably, you was thinking > 'D' as in 'Debug' for the FWSPID naming. I suspect it was also to do with some lack of detail in the early data sheets :) > >> Actually, I think it's worth squashing this with 3/5 so it's a proper >> fix rather than separate remove/add? > > Two reasons I separated them. > 1. Author is different. > 2. 2/5 is a bug fix and 3/5 introduces a new pinmux. Okay, I'm not terribly fussed. > >>> FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); >>> FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); >>> /* >>> @@ -1918,7 +1911,6 @@ static const struct aspeed_pin_group >>> aspeed_g6_groups[] = { >>> ASPEED_PINCTRL_GROUP(FSI2), >>> ASPEED_PINCTRL_GROUP(FWSPIABR), >>> ASPEED_PINCTRL_GROUP(FWSPID), >>> - ASPEED_PINCTRL_GROUP(FWQSPID), >> >> We should also remove the function (not just the group). > > Still worth to keep FWSPID to support SCU500[3] - Boot from debug SPI. > FWSPID would work on single and dual data mode only. I guess, yeah, though the only use case I see for it is a temporary devicetree change to account for someone setting the strap pin into the debug state. I don't see a reason to support it beyond that, but that said we still need to support it for that use case. Andrew ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl 2022-03-28 23:01 ` Andrew Jeffery @ 2022-03-28 23:12 ` Jae Hyun Yoo 0 siblings, 0 replies; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-28 23:12 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On 3/28/2022 4:01 PM, Andrew Jeffery wrote: > > > On Tue, 29 Mar 2022, at 01:11, Jae Hyun Yoo wrote: >> On 3/27/2022 8:18 PM, Andrew Jeffery wrote: >>> >>> >>> On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >>>> FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove >>>> FWQSPID group in pinctrl. These pins must be used with the FWSPI >>>> pins that are dedicated for boot SPI interface which provides >>>> same 3.3v logic level. >>>> >>>> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >>>> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") >>>> --- >>>> Changes in v2: >>>> * None. >>>> >>>> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 14 +++----------- >>>> 1 file changed, 3 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>>> b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>>> index a3fa03bcd9a3..54064714d73f 100644 >>>> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>>> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >>>> @@ -1236,18 +1236,12 @@ FUNC_GROUP_DECL(SALT8, AA12); >>>> FUNC_GROUP_DECL(WDTRST4, AA12); >>>> >>>> #define AE12 196 >>>> -SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, >>>> - SIG_DESC_SET(SCU438, 4)); >>>> SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); >>>> -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), >>>> - SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >>>> +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >>>> >>>> #define AF12 197 >>>> -SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, >>>> - SIG_DESC_SET(SCU438, 5)); >>>> SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); >>>> -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), >>>> - SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >>>> +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >>>> >>>> #define AC12 198 >>>> SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); >>>> @@ -1520,9 +1514,8 @@ SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, >>>> EMMC, SIG_DESC_SET(SCU404, 3)); >>>> PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); >>>> >>>> GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); >>>> -GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); >>>> GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, >>>> Y4); >>>> -FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); >>>> +FUNC_DECL_1(FWSPID, FWSPID); >>> >>> Really this is the FWSPI18 group now? The FWSPID name never made sense. >>> I'm not sure what I was thinking. >> >> Yes, it's now the FWSPI18 which is described as 'debug SPI' in the >> datasheet. Corresponding SCU500[3] bit is also described as that 'the >> bit is for verification and testing only'. Probably, you was thinking >> 'D' as in 'Debug' for the FWSPID naming. > > I suspect it was also to do with some lack of detail in the early data sheets :) Right, there were lots of lack of detail in the early version of AST2600 datasheets and FWSPI18 description is still insufficient even in the latest version, IMO. >> >>> Actually, I think it's worth squashing this with 3/5 so it's a proper >>> fix rather than separate remove/add? >> >> Two reasons I separated them. >> 1. Author is different. >> 2. 2/5 is a bug fix and 3/5 introduces a new pinmux. > > Okay, I'm not terribly fussed. Thanks! I'll keep them separated. > >> >>>> FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); >>>> FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); >>>> /* >>>> @@ -1918,7 +1911,6 @@ static const struct aspeed_pin_group >>>> aspeed_g6_groups[] = { >>>> ASPEED_PINCTRL_GROUP(FSI2), >>>> ASPEED_PINCTRL_GROUP(FWSPIABR), >>>> ASPEED_PINCTRL_GROUP(FWSPID), >>>> - ASPEED_PINCTRL_GROUP(FWQSPID), >>> >>> We should also remove the function (not just the group). >> >> Still worth to keep FWSPID to support SCU500[3] - Boot from debug SPI. >> FWSPID would work on single and dual data mode only. > > I guess, yeah, though the only use case I see for it is a temporary > devicetree change to account for someone setting the strap pin into the > debug state. I don't see a reason to support it beyond that, but that said > we still need to support it for that use case. Great! I'll keep FWSPID as supported. I'll send v3 soon. Thanks a lot for your review! -Jae ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group 2022-03-25 15:40 [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl Jae Hyun Yoo @ 2022-03-25 15:40 ` Jae Hyun Yoo 2022-03-28 3:15 ` Andrew Jeffery 2022-03-25 15:40 ` [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Jae Hyun Yoo 4 siblings, 1 reply; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-25 15:40 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Johnny Huang, Jae Hyun Yoo From: Johnny Huang <johnny_huang@aspeedtech.com> Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> --- Changes in v2: * None. drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 54064714d73f..80838dc54b3a 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1236,12 +1236,17 @@ FUNC_GROUP_DECL(SALT8, AA12); FUNC_GROUP_DECL(WDTRST4, AA12); #define AE12 196 +SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4)); SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2), + SIG_EXPR_LIST_PTR(AE12, GPIOY4)); #define AF12 197 +SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5)); SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3), + SIG_EXPR_LIST_PTR(AF12, GPIOY5)); +FUNC_GROUP_DECL(FWQSPI, AE12, AF12); #define AC12 198 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); @@ -1911,6 +1916,7 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(FSI2), ASPEED_PINCTRL_GROUP(FWSPIABR), ASPEED_PINCTRL_GROUP(FWSPID), + ASPEED_PINCTRL_GROUP(FWQSPI), ASPEED_PINCTRL_GROUP(FWSPIWP), ASPEED_PINCTRL_GROUP(GPIT0), ASPEED_PINCTRL_GROUP(GPIT1), @@ -2152,6 +2158,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(FSI2), ASPEED_PINCTRL_FUNC(FWSPIABR), ASPEED_PINCTRL_FUNC(FWSPID), + ASPEED_PINCTRL_FUNC(FWQSPI), ASPEED_PINCTRL_FUNC(FWSPIWP), ASPEED_PINCTRL_FUNC(GPIT0), ASPEED_PINCTRL_FUNC(GPIT1), -- 2.25.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group 2022-03-25 15:40 ` [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Jae Hyun Yoo @ 2022-03-28 3:15 ` Andrew Jeffery 2022-03-28 14:26 ` Jae Hyun Yoo 0 siblings, 1 reply; 18+ messages in thread From: Andrew Jeffery @ 2022-03-28 3:15 UTC (permalink / raw) To: Jae Hyun Yoo, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Johnny Huang On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: > From: Johnny Huang <johnny_huang@aspeedtech.com> > > Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support > AST2600 FW SPI quad mode. These pins can be used with dedicated FW > SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) > and FWSPIMISO (AB13). > > Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> > Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> > --- > Changes in v2: > * None. > > drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > index 54064714d73f..80838dc54b3a 100644 > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > @@ -1236,12 +1236,17 @@ FUNC_GROUP_DECL(SALT8, AA12); > FUNC_GROUP_DECL(WDTRST4, AA12); > > #define AE12 196 > +SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4)); > SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); > -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); > +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2), > + SIG_EXPR_LIST_PTR(AE12, GPIOY4)); > > #define AF12 197 > +SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5)); > SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); > -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); > +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3), > + SIG_EXPR_LIST_PTR(AF12, GPIOY5)); > +FUNC_GROUP_DECL(FWQSPI, AE12, AF12); > > #define AC12 198 > SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); > @@ -1911,6 +1916,7 @@ static const struct aspeed_pin_group > aspeed_g6_groups[] = { > ASPEED_PINCTRL_GROUP(FSI2), > ASPEED_PINCTRL_GROUP(FWSPIABR), > ASPEED_PINCTRL_GROUP(FWSPID), > + ASPEED_PINCTRL_GROUP(FWQSPI), > ASPEED_PINCTRL_GROUP(FWSPIWP), > ASPEED_PINCTRL_GROUP(GPIT0), > ASPEED_PINCTRL_GROUP(GPIT1), > @@ -2152,6 +2158,7 @@ static const struct aspeed_pin_function > aspeed_g6_functions[] = { > ASPEED_PINCTRL_FUNC(FSI2), > ASPEED_PINCTRL_FUNC(FWSPIABR), > ASPEED_PINCTRL_FUNC(FWSPID), > + ASPEED_PINCTRL_FUNC(FWQSPI), You need to update the binding documentation as well. Andrew ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group 2022-03-28 3:15 ` Andrew Jeffery @ 2022-03-28 14:26 ` Jae Hyun Yoo 0 siblings, 0 replies; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-28 14:26 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Johnny Huang On 3/27/2022 8:15 PM, Andrew Jeffery wrote: > > > On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >> From: Johnny Huang <johnny_huang@aspeedtech.com> >> >> Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support >> AST2600 FW SPI quad mode. These pins can be used with dedicated FW >> SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) >> and FWSPIMISO (AB13). >> >> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> >> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >> --- >> Changes in v2: >> * None. >> >> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 11 +++++++++-- >> 1 file changed, 9 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> index 54064714d73f..80838dc54b3a 100644 >> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c >> @@ -1236,12 +1236,17 @@ FUNC_GROUP_DECL(SALT8, AA12); >> FUNC_GROUP_DECL(WDTRST4, AA12); >> >> #define AE12 196 >> +SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4)); >> SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); >> -PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >> +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2), >> + SIG_EXPR_LIST_PTR(AE12, GPIOY4)); >> >> #define AF12 197 >> +SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5)); >> SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); >> -PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >> +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3), >> + SIG_EXPR_LIST_PTR(AF12, GPIOY5)); >> +FUNC_GROUP_DECL(FWQSPI, AE12, AF12); >> >> #define AC12 198 >> SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); >> @@ -1911,6 +1916,7 @@ static const struct aspeed_pin_group >> aspeed_g6_groups[] = { >> ASPEED_PINCTRL_GROUP(FSI2), >> ASPEED_PINCTRL_GROUP(FWSPIABR), >> ASPEED_PINCTRL_GROUP(FWSPID), >> + ASPEED_PINCTRL_GROUP(FWQSPI), >> ASPEED_PINCTRL_GROUP(FWSPIWP), >> ASPEED_PINCTRL_GROUP(GPIT0), >> ASPEED_PINCTRL_GROUP(GPIT1), >> @@ -2152,6 +2158,7 @@ static const struct aspeed_pin_function >> aspeed_g6_functions[] = { >> ASPEED_PINCTRL_FUNC(FSI2), >> ASPEED_PINCTRL_FUNC(FWSPIABR), >> ASPEED_PINCTRL_FUNC(FWSPID), >> + ASPEED_PINCTRL_FUNC(FWQSPI), > > You need to update the binding documentation as well. Will do it in v3. Thanks, Jae ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi 2022-03-25 15:40 [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo ` (2 preceding siblings ...) 2022-03-25 15:40 ` [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Jae Hyun Yoo @ 2022-03-25 15:40 ` Jae Hyun Yoo 2022-03-28 3:17 ` Andrew Jeffery 2022-03-25 15:40 ` [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Jae Hyun Yoo 4 siblings, 1 reply; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-25 15:40 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Johnny Huang, Jae Hyun Yoo From: Johnny Huang <johnny_huang@aspeedtech.com> Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0#, FWSPICK, FWSPIMOSI and FWSPIMISO. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> --- Changes in v2: * None. arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 06d60a8540e9..47c3fb137cbc 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -117,6 +117,11 @@ pinctrl_fwspid_default: fwspid_default { groups = "FWSPID"; }; + pinctrl_fwqspi_default: fwqspi_default { + function = "FWQSPI"; + groups = "FWQSPI"; + }; + pinctrl_fwspiwp_default: fwspiwp_default { function = "FWSPIWP"; groups = "FWSPIWP"; -- 2.25.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi 2022-03-25 15:40 ` [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi Jae Hyun Yoo @ 2022-03-28 3:17 ` Andrew Jeffery 2022-03-28 14:42 ` Jae Hyun Yoo 0 siblings, 1 reply; 18+ messages in thread From: Andrew Jeffery @ 2022-03-28 3:17 UTC (permalink / raw) To: Jae Hyun Yoo, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Johnny Huang On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: > From: Johnny Huang <johnny_huang@aspeedtech.com> > > Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode. > These pins can be used with dedicated FW SPI pins - FWSPICS0#, > FWSPICK, FWSPIMOSI and FWSPIMISO. > > Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> > Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> > --- > Changes in v2: > * None. > > arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi > b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi > index 06d60a8540e9..47c3fb137cbc 100644 > --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi > +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi > @@ -117,6 +117,11 @@ pinctrl_fwspid_default: fwspid_default { > groups = "FWSPID"; > }; > > + pinctrl_fwqspi_default: fwqspi_default { > + function = "FWQSPI"; > + groups = "FWQSPI"; > + }; > + This is okay once you update the binding documentation. Andrew ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi 2022-03-28 3:17 ` Andrew Jeffery @ 2022-03-28 14:42 ` Jae Hyun Yoo 0 siblings, 0 replies; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-28 14:42 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Johnny Huang On 3/27/2022 8:17 PM, Andrew Jeffery wrote: > > > On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >> From: Johnny Huang <johnny_huang@aspeedtech.com> >> >> Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode. >> These pins can be used with dedicated FW SPI pins - FWSPICS0#, >> FWSPICK, FWSPIMOSI and FWSPIMISO. >> >> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> >> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >> --- >> Changes in v2: >> * None. >> >> arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi >> b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi >> index 06d60a8540e9..47c3fb137cbc 100644 >> --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi >> +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi >> @@ -117,6 +117,11 @@ pinctrl_fwspid_default: fwspid_default { >> groups = "FWSPID"; >> }; >> >> + pinctrl_fwqspi_default: fwqspi_default { >> + function = "FWQSPI"; >> + groups = "FWQSPI"; >> + }; >> + > > This is okay once you update the binding documentation. Will add a bindings patch in v3. Thanks, Jae > Andrew ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group 2022-03-25 15:40 [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo ` (3 preceding siblings ...) 2022-03-25 15:40 ` [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi Jae Hyun Yoo @ 2022-03-25 15:40 ` Jae Hyun Yoo 2022-03-28 3:16 ` Andrew Jeffery 4 siblings, 1 reply; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-25 15:40 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed, Jae Hyun Yoo Fix incorrect function mappings in pinctrl_qspi1_default and pinctrl_qspi2_default since there function should be SPI1 and SPI2 respectively. Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes") --- Changes in v2: * None. arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 47c3fb137cbc..7cd4f075e325 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -653,12 +653,12 @@ pinctrl_pwm9g1_default: pwm9g1_default { }; pinctrl_qspi1_default: qspi1_default { - function = "QSPI1"; + function = "SPI1"; groups = "QSPI1"; }; pinctrl_qspi2_default: qspi2_default { - function = "QSPI2"; + function = "SPI2"; groups = "QSPI2"; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group 2022-03-25 15:40 ` [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Jae Hyun Yoo @ 2022-03-28 3:16 ` Andrew Jeffery 2022-03-28 14:43 ` Jae Hyun Yoo 0 siblings, 1 reply; 18+ messages in thread From: Andrew Jeffery @ 2022-03-28 3:16 UTC (permalink / raw) To: Jae Hyun Yoo, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: > Fix incorrect function mappings in pinctrl_qspi1_default and > pinctrl_qspi2_default since there function should be SPI1 and > SPI2 respectively. > > Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> > Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group 2022-03-28 3:16 ` Andrew Jeffery @ 2022-03-28 14:43 ` Jae Hyun Yoo 0 siblings, 0 replies; 18+ messages in thread From: Jae Hyun Yoo @ 2022-03-28 14:43 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Joel Stanley, Andrew Lunn Cc: Jamie Iles, Graeme Gregory, devicetree, linux-arm-kernel, linux-aspeed On 3/27/2022 8:16 PM, Andrew Jeffery wrote: > > > On Sat, 26 Mar 2022, at 02:10, Jae Hyun Yoo wrote: >> Fix incorrect function mappings in pinctrl_qspi1_default and >> pinctrl_qspi2_default since there function should be SPI1 and >> SPI2 respectively. >> >> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> >> Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes") > > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Thanks for your review! -Jae ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-03-28 23:12 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-25 15:40 [PATCH v2 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi Jae Hyun Yoo 2022-03-28 3:09 ` Andrew Jeffery 2022-03-28 14:26 ` Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 2/5] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl Jae Hyun Yoo 2022-03-28 3:18 ` Andrew Jeffery 2022-03-28 14:41 ` Jae Hyun Yoo 2022-03-28 23:01 ` Andrew Jeffery 2022-03-28 23:12 ` Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Jae Hyun Yoo 2022-03-28 3:15 ` Andrew Jeffery 2022-03-28 14:26 ` Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi Jae Hyun Yoo 2022-03-28 3:17 ` Andrew Jeffery 2022-03-28 14:42 ` Jae Hyun Yoo 2022-03-25 15:40 ` [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Jae Hyun Yoo 2022-03-28 3:16 ` Andrew Jeffery 2022-03-28 14:43 ` Jae Hyun Yoo
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