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From: Matthew Hagan <mnhagan88@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>, Jakub Kicinski <kuba@kernel.org>
Cc: Vivien Didelot <vivien.didelot@gmail.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	linux@armlinux.org.uk, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org, John Crispin <john@phrozen.org>,
	Jonathan McDowell <noodles@earth.li>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: Add PORT0_PAD_CTRL properties
Date: Fri, 17 Jul 2020 20:26:02 +0100	[thread overview]
Message-ID: <c86c4da0-a740-55cc-33dd-7a91e36c7738@gmail.com> (raw)
In-Reply-To: <20200716223236.GA1314837@lunn.ch>



On 16/07/2020 23:32, Andrew Lunn wrote:
> On Thu, Jul 16, 2020 at 03:09:25PM -0700, Jakub Kicinski wrote:
>> On Mon, 13 Jul 2020 21:50:26 +0100 Matthew Hagan wrote:
>>> Add names and decriptions of additional PORT0_PAD_CTRL properties.
>>>
>>> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
>>> ---
>>>  Documentation/devicetree/bindings/net/dsa/qca8k.txt | 8 ++++++++
>>>  1 file changed, 8 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
>>> index ccbc6d89325d..3d34c4f2e891 100644
>>> --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
>>> +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
>>> @@ -13,6 +13,14 @@ Optional properties:
>>>  
>>>  - reset-gpios: GPIO to be used to reset the whole device
>>>  
>>> +Optional MAC configuration properties:
>>> +
>>> +- qca,exchange-mac0-mac6:	If present, internally swaps MAC0 and MAC6.
>>
>> Perhaps we can say a little more here?
>>
>>> +- qca,sgmii-rxclk-falling-edge:	If present, sets receive clock phase to
>>> +				falling edge.
>>> +- qca,sgmii-txclk-falling-edge:	If present, sets transmit clock phase to
>>> +				falling edge.
>>
>> These are not something that other vendors may implement and therefore
>> something we may want to make generic? Andrew?
> 
> I've never seen any other vendor implement this. Which to me makes me
> think this is a vendor extension, to Ciscos vendor extension of
> 1000BaseX.
> 
> Matthew, do you have a real use cases of these? I don't see a DT patch
> making use of them. And if you do, what is the PHY on the other end
> which also allows you to invert the clocks?
> 
The use case I am working on is the Cisco Meraki MX65 which requires bit
18 set (qca,sgmii-txclk-falling-edge). On the other side is a BCM58625
SRAB with ports 4 and 5 in SGMII mode. There is no special polarity
configuration set on this side though I do have very limited info on
what is available. The settings I have replicate the vendor
configuration extracted from the device.

The qca,sgmii-rxclk-falling-edge option (bit 19) is commonly used
according to the device trees found in the OpenWrt, which is still using
the ar8216 driver. With a count through the ar8327-initvals I see bit 19
set on 18 of 22 devices using SGMII on MAC0.
>        Andrew
> 

Matthew

  reply	other threads:[~2020-07-17 19:26 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <2e1776f997441792a44cd35a16f1e69f848816ce.1594668793.git.mnhagan88@gmail.com>
2020-07-13 20:50 ` [PATCH 2/2] dt-bindings: net: dsa: qca8k: Add PORT0_PAD_CTRL properties Matthew Hagan
2020-07-16 22:09   ` Jakub Kicinski
2020-07-16 22:32     ` Andrew Lunn
2020-07-17 19:26       ` Matthew Hagan [this message]
2020-07-17 20:02         ` Florian Fainelli
2020-07-18 13:00         ` Vladimir Oltean
2020-07-21  1:59         ` Rob Herring
2020-07-16 22:38     ` Vladimir Oltean
2020-07-17  7:49       ` Jonathan McDowell
2020-07-17 20:29     ` Matthew Hagan
2020-07-17 20:39       ` Florian Fainelli
2020-07-17 20:48         ` John Crispin
2020-07-17 20:44       ` John Crispin
2020-07-18 13:20         ` Russell King - ARM Linux admin
2020-07-18 14:44           ` Andrew Lunn
2020-07-18 15:08             ` Russell King - ARM Linux admin
2020-07-18 15:34           ` Matthew Hagan
2020-07-16 22:19   ` Florian Fainelli

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