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[212.159.108.31]) by smtp.gmail.com with ESMTPSA id g145sm20090812wmg.23.2020.07.17.12.26.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jul 2020 12:26:04 -0700 (PDT) Subject: Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: Add PORT0_PAD_CTRL properties To: Andrew Lunn , Jakub Kicinski Cc: Vivien Didelot , Florian Fainelli , "David S. Miller" , linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, John Crispin , Jonathan McDowell , Rob Herring , devicetree@vger.kernel.org References: <2e1776f997441792a44cd35a16f1e69f848816ce.1594668793.git.mnhagan88@gmail.com> <20200716150925.0f3e01b8@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> <20200716223236.GA1314837@lunn.ch> From: Matthew Hagan Message-ID: Date: Fri, 17 Jul 2020 20:26:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200716223236.GA1314837@lunn.ch> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 16/07/2020 23:32, Andrew Lunn wrote: > On Thu, Jul 16, 2020 at 03:09:25PM -0700, Jakub Kicinski wrote: >> On Mon, 13 Jul 2020 21:50:26 +0100 Matthew Hagan wrote: >>> Add names and decriptions of additional PORT0_PAD_CTRL properties. >>> >>> Signed-off-by: Matthew Hagan >>> --- >>> Documentation/devicetree/bindings/net/dsa/qca8k.txt | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt >>> index ccbc6d89325d..3d34c4f2e891 100644 >>> --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt >>> +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt >>> @@ -13,6 +13,14 @@ Optional properties: >>> >>> - reset-gpios: GPIO to be used to reset the whole device >>> >>> +Optional MAC configuration properties: >>> + >>> +- qca,exchange-mac0-mac6: If present, internally swaps MAC0 and MAC6. >> >> Perhaps we can say a little more here? >> >>> +- qca,sgmii-rxclk-falling-edge: If present, sets receive clock phase to >>> + falling edge. >>> +- qca,sgmii-txclk-falling-edge: If present, sets transmit clock phase to >>> + falling edge. >> >> These are not something that other vendors may implement and therefore >> something we may want to make generic? Andrew? > > I've never seen any other vendor implement this. Which to me makes me > think this is a vendor extension, to Ciscos vendor extension of > 1000BaseX. > > Matthew, do you have a real use cases of these? I don't see a DT patch > making use of them. And if you do, what is the PHY on the other end > which also allows you to invert the clocks? > The use case I am working on is the Cisco Meraki MX65 which requires bit 18 set (qca,sgmii-txclk-falling-edge). On the other side is a BCM58625 SRAB with ports 4 and 5 in SGMII mode. There is no special polarity configuration set on this side though I do have very limited info on what is available. The settings I have replicate the vendor configuration extracted from the device. The qca,sgmii-rxclk-falling-edge option (bit 19) is commonly used according to the device trees found in the OpenWrt, which is still using the ar8216 driver. With a count through the ar8327-initvals I see bit 19 set on 18 of 22 devices using SGMII on MAC0. > Andrew > Matthew