[PATCH v4 0/3] Add JH7110 cpufreq support

[PATCH v4 0/3] Add JH7110 cpufreq support

[Mason Huo]

The StarFive JH7110 SoC has four RISC-V cores,
and it supports up to 4 cpu frequency loads.

This patchset adds the compatible strings into the allowlist
for supporting the generic cpufreq driver on JH7110 SoC.
Also, it enables the axp15060 pmic for the cpu power source.

The series has been tested on the VisionFive 2 boards which
are equipped with JH7110 SoC and axp15060 pmic.

---
This patchset is based on v6.4-rc4 with these patches applied:
[1] ("regulator: Add X-Powers AXP15060/AXP313a PMIC support")
    https://lore.kernel.org/lkml/20230524000012.15028-1-andre.przywara@arm.com/

Changes since v3:
- Fix the dtb_check issues for axp15060 pmic dts configuration.

Changes since v2:
- Fix the new blank line at EOF issue in dtsi.

Changes since v1:
- Fix dts node naming issues.
- Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
- Follow the alphabetical order to place the cpufreq dt allowlist.

Mason Huo (3):
  riscv: dts: starfive: Enable axp15060 pmic for cpufreq
  cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
  riscv: dts: starfive: Add cpu scaling for JH7110 SoC

 .../jh7110-starfive-visionfive-2.dtsi         | 33 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 33 +++++++++++++++++++
 drivers/cpufreq/cpufreq-dt-platdev.c          |  2 ++
 3 files changed, 68 insertions(+)

-- 
2.39.2

[PATCH v4 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq

[Mason Huo]

The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
 .../starfive/jh7110-starfive-visionfive-2.dtsi  | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..9714da5550d7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -114,6 +114,23 @@ &i2c5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c5_pins>;
 	status = "okay";
+
+	axp15060: pmic@36 {
+		compatible = "x-powers,axp15060";
+		reg = <0x36>;
+		interrupts = <0>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		regulators {
+			vdd_cpu: dcdc2 {
+				regulator-always-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1540000>;
+				regulator-name = "vdd-cpu";
+			};
+		};
+	};
 };
 
 &i2c6 {
-- 
2.39.2

Re: [PATCH v4 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq

[Bo Gan]

On 6/6/23 3:56 AM, Mason Huo wrote:
> The VisionFive 2 board has an embedded pmic axp15060,
> which supports the cpu DVFS through the dcdc2 regulator.
> This patch enables axp15060 pmic and configs the dcdc2.
> 
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
>   .../starfive/jh7110-starfive-visionfive-2.dtsi  | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 2a6d81609284..9714da5550d7 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -114,6 +114,23 @@ &i2c5 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&i2c5_pins>;
>   	status = "okay";
> +
> +	axp15060: pmic@36 {
> +		compatible = "x-powers,axp15060";
> +		reg = <0x36>;
> +		interrupts = <0>;
> +		interrupt-controller;

This appears to be wrong. I'm working on a private tree of OpenSBI, where I validate
all PLIC SYS/AON/STG CRG/SYSCON/IOMUX, and other devices... register reads/writes.
Looks like this `interrupts = <0>` will cause the kernel code (my vanilla 6.6 tree)
to enable interrupt 0 on PLIC, which is wrong. Of course, you won't see this problem
if you run upstream OpenSBI, where all writes to PLIC are permitted. I assume PLIC
will ignore this request to enable irq 0. Still, this is wrong. Can someone from
Starfive take this issue? Attaching the backtrace here:

# This line is from my OpenSBI
jh7110_virt_plic_write: U7 refusing to enable interrupt 0
# After this, I'll inject a memory access (write) fault to S mode

# Below is from Linux
Oops - store (or AMO) access fault [#1]
Modules linked in:
CPU: 0 PID: 62 Comm: kworker/u9:2 Not tainted 6.6.0-gc3eb9993b167 #14
Hardware name: StarFive VisionFive 2 v1.3B (DT)
Workqueue: events_unbound deferred_probe_work_func
epc : plic_irq_enable+0xd2/0x15e
  ra : plic_irq_enable+0xa8/0x15e
epc : ffffffff804650bc ra : ffffffff80465092 sp : ffffffc8003f34c0
  gp : ffffffff816d2290 tp : ffffffd802411f80 t0 : ffffffc8003f3010
  t1 : 0000000000000001 t2 : 0000000000000003 s0 : ffffffc8003f3530
  s1 : ffffffd801eaee30 a0 : ffffffd8bff835b0 a1 : 000000000000001e
  a2 : 0000000000000004 a3 : ffffffd801eaee00 a4 : 000000000000001e
  a5 : ffffffc804002100 a6 : 0000000000000000 a7 : 00000000000007ad
  s2 : ffffffff80ede5a0 s3 : 0000000000000001 s4 : 000000000000ffff
  s5 : 00000000ffffffff s6 : 0000000000000000 s7 : 000000000000001f
  s8 : ffffffff81707af0 s9 : ffffffff80eda688 s10: ffffffd801eaee00
  s11: ffffffd8bff835a0 t3 : ffffffff816d3420 t4 : 0000000000000002
  t5 : 0000000000000000 t6 : 0000000000000000
status: 0000000200000100 badaddr: ffffffc804002100 cause: 0000000000000007
[<ffffffff804650bc>] plic_irq_enable+0xd2/0x15e
[<ffffffff800649e6>] irq_enable+0x2c/0x64
[<ffffffff80064a76>] __irq_startup+0x58/0x60
[<ffffffff80064ada>] irq_startup+0x5c/0x14e
[<ffffffff800621f4>] __setup_irq+0x582/0x644
[<ffffffff80062368>] request_threaded_irq+0xb2/0x154
[<ffffffff8055571a>] regmap_add_irq_chip_fwnode+0x6fe/0x8f2
[<ffffffff80555944>] regmap_add_irq_chip+0x36/0x4a
[<ffffffff8055cb1e>] axp20x_device_probe+0x36/0x114
[<ffffffff8055cce6>] axp20x_i2c_probe+0x6c/0xa0
[<ffffffff8063a8f0>] i2c_device_probe+0x11c/0x23e
[<ffffffff80533464>] really_probe+0x86/0x23e
[<ffffffff80533678>] __driver_probe_device+0x5c/0xda
[<ffffffff80533722>] driver_probe_device+0x2c/0xf8
[<ffffffff8053385c>] __device_attach_driver+0x6e/0xd0
[<ffffffff80531a2c>] bus_for_each_drv+0x5a/0x9a
[<ffffffff80533ba0>] __device_attach+0x78/0x116
[<ffffffff80533db6>] device_initial_probe+0xe/0x16
[<ffffffff80532722>] bus_probe_device+0x86/0x88
[<ffffffff8053034a>] device_add+0x3b2/0x552
[<ffffffff80530500>] device_register+0x16/0x20
[<ffffffff8063bb54>] i2c_new_client_device+0x14e/0x214
[<ffffffff8063d9ae>] of_i2c_register_devices+0xa2/0xf8
[<ffffffff8063c246>] i2c_register_adapter+0x130/0x32e
[<ffffffff8063c49e>] __i2c_add_numbered_adapter+0x5a/0x86
[<ffffffff8063c55a>] i2c_add_adapter+0x90/0xb4
[<ffffffff8063c62e>] i2c_add_numbered_adapter+0x22/0x2a
[<ffffffff8063fd34>] i2c_dw_probe_master+0x288/0x304
[<ffffffff806409c4>] dw_i2c_plat_probe+0x288/0x37e
[<ffffffff80535946>] platform_probe+0x4e/0xa6
[<ffffffff80533464>] really_probe+0x86/0x23e
[<ffffffff80533678>] __driver_probe_device+0x5c/0xda
[<ffffffff80533722>] driver_probe_device+0x2c/0xf8
[<ffffffff8053385c>] __device_attach_driver+0x6e/0xd0
[<ffffffff80531a2c>] bus_for_each_drv+0x5a/0x9a
[<ffffffff80533ba0>] __device_attach+0x78/0x116
[<ffffffff80533db6>] device_initial_probe+0xe/0x16
[<ffffffff80532722>] bus_probe_device+0x86/0x88
[<ffffffff80532b86>] deferred_probe_work_func+0x70/0xa6
[<ffffffff800238c2>] process_one_work+0x14a/0x23a
[<ffffffff80024760>] worker_thread+0x314/0x450
[<ffffffff8002be5a>] kthread+0x9a/0xae
[<ffffffff8000248a>] ret_from_fork+0xa/0x1c
Code: 97ba 000f 0140 4398 000f 08a0 9bbb 0179 ebb3 00eb (a023) 0177
---[ end trace 0000000000000000 ]---


> +		#interrupt-cells = <1>;
> +
> +		regulators {
> +			vdd_cpu: dcdc2 {
> +				regulator-always-on;
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1540000>;
> +				regulator-name = "vdd-cpu";
> +			};
> +		};
> +	};
>   };
>   
>   &i2c6 {
> 

Bo

Re: [PATCH v4 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq

[Shengyu Qu]

[-- Attachment #1.1.1: Type: text/plain, Size: 6342 bytes --]

Hi Bo,

Since commit b2cb2ae22278f1918f7526b89760ee00b4a81393 ("mfd: axp20x:
Generalise handling without interrupt"), the "interrupts = <0>;" line
can be removed. It was kept to fix a driver issue that driver would try
to find an IRQ line for power button function of the PMIC.

I'll send a patch to fix it.

Best Regards,
Shengyu

在 2024/3/5 16:23, Bo Gan 写道:
> On 6/6/23 3:56 AM, Mason Huo wrote:
>> The VisionFive 2 board has an embedded pmic axp15060,
>> which supports the cpu DVFS through the dcdc2 regulator.
>> This patch enables axp15060 pmic and configs the dcdc2.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>>   .../starfive/jh7110-starfive-visionfive-2.dtsi  | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>>
>> diff --git 
>> a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi 
>> b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..9714da5550d7 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -114,6 +114,23 @@ &i2c5 {
>>       pinctrl-names = "default";
>>       pinctrl-0 = <&i2c5_pins>;
>>       status = "okay";
>> +
>> +    axp15060: pmic@36 {
>> +        compatible = "x-powers,axp15060";
>> +        reg = <0x36>;
>> +        interrupts = <0>;
>> +        interrupt-controller;
> 
> This appears to be wrong. I'm working on a private tree of OpenSBI, 
> where I validate
> all PLIC SYS/AON/STG CRG/SYSCON/IOMUX, and other devices... register 
> reads/writes.
> Looks like this `interrupts = <0>` will cause the kernel code (my 
> vanilla 6.6 tree)
> to enable interrupt 0 on PLIC, which is wrong. Of course, you won't see 
> this problem
> if you run upstream OpenSBI, where all writes to PLIC are permitted. I 
> assume PLIC
> will ignore this request to enable irq 0. Still, this is wrong. Can 
> someone from
> Starfive take this issue? Attaching the backtrace here:
> 
> # This line is from my OpenSBI
> jh7110_virt_plic_write: U7 refusing to enable interrupt 0
> # After this, I'll inject a memory access (write) fault to S mode
> 
> # Below is from Linux
> Oops - store (or AMO) access fault [#1]
> Modules linked in:
> CPU: 0 PID: 62 Comm: kworker/u9:2 Not tainted 6.6.0-gc3eb9993b167 #14
> Hardware name: StarFive VisionFive 2 v1.3B (DT)
> Workqueue: events_unbound deferred_probe_work_func
> epc : plic_irq_enable+0xd2/0x15e
>   ra : plic_irq_enable+0xa8/0x15e
> epc : ffffffff804650bc ra : ffffffff80465092 sp : ffffffc8003f34c0
>   gp : ffffffff816d2290 tp : ffffffd802411f80 t0 : ffffffc8003f3010
>   t1 : 0000000000000001 t2 : 0000000000000003 s0 : ffffffc8003f3530
>   s1 : ffffffd801eaee30 a0 : ffffffd8bff835b0 a1 : 000000000000001e
>   a2 : 0000000000000004 a3 : ffffffd801eaee00 a4 : 000000000000001e
>   a5 : ffffffc804002100 a6 : 0000000000000000 a7 : 00000000000007ad
>   s2 : ffffffff80ede5a0 s3 : 0000000000000001 s4 : 000000000000ffff
>   s5 : 00000000ffffffff s6 : 0000000000000000 s7 : 000000000000001f
>   s8 : ffffffff81707af0 s9 : ffffffff80eda688 s10: ffffffd801eaee00
>   s11: ffffffd8bff835a0 t3 : ffffffff816d3420 t4 : 0000000000000002
>   t5 : 0000000000000000 t6 : 0000000000000000
> status: 0000000200000100 badaddr: ffffffc804002100 cause: 0000000000000007
> [<ffffffff804650bc>] plic_irq_enable+0xd2/0x15e
> [<ffffffff800649e6>] irq_enable+0x2c/0x64
> [<ffffffff80064a76>] __irq_startup+0x58/0x60
> [<ffffffff80064ada>] irq_startup+0x5c/0x14e
> [<ffffffff800621f4>] __setup_irq+0x582/0x644
> [<ffffffff80062368>] request_threaded_irq+0xb2/0x154
> [<ffffffff8055571a>] regmap_add_irq_chip_fwnode+0x6fe/0x8f2
> [<ffffffff80555944>] regmap_add_irq_chip+0x36/0x4a
> [<ffffffff8055cb1e>] axp20x_device_probe+0x36/0x114
> [<ffffffff8055cce6>] axp20x_i2c_probe+0x6c/0xa0
> [<ffffffff8063a8f0>] i2c_device_probe+0x11c/0x23e
> [<ffffffff80533464>] really_probe+0x86/0x23e
> [<ffffffff80533678>] __driver_probe_device+0x5c/0xda
> [<ffffffff80533722>] driver_probe_device+0x2c/0xf8
> [<ffffffff8053385c>] __device_attach_driver+0x6e/0xd0
> [<ffffffff80531a2c>] bus_for_each_drv+0x5a/0x9a
> [<ffffffff80533ba0>] __device_attach+0x78/0x116
> [<ffffffff80533db6>] device_initial_probe+0xe/0x16
> [<ffffffff80532722>] bus_probe_device+0x86/0x88
> [<ffffffff8053034a>] device_add+0x3b2/0x552
> [<ffffffff80530500>] device_register+0x16/0x20
> [<ffffffff8063bb54>] i2c_new_client_device+0x14e/0x214
> [<ffffffff8063d9ae>] of_i2c_register_devices+0xa2/0xf8
> [<ffffffff8063c246>] i2c_register_adapter+0x130/0x32e
> [<ffffffff8063c49e>] __i2c_add_numbered_adapter+0x5a/0x86
> [<ffffffff8063c55a>] i2c_add_adapter+0x90/0xb4
> [<ffffffff8063c62e>] i2c_add_numbered_adapter+0x22/0x2a
> [<ffffffff8063fd34>] i2c_dw_probe_master+0x288/0x304
> [<ffffffff806409c4>] dw_i2c_plat_probe+0x288/0x37e
> [<ffffffff80535946>] platform_probe+0x4e/0xa6
> [<ffffffff80533464>] really_probe+0x86/0x23e
> [<ffffffff80533678>] __driver_probe_device+0x5c/0xda
> [<ffffffff80533722>] driver_probe_device+0x2c/0xf8
> [<ffffffff8053385c>] __device_attach_driver+0x6e/0xd0
> [<ffffffff80531a2c>] bus_for_each_drv+0x5a/0x9a
> [<ffffffff80533ba0>] __device_attach+0x78/0x116
> [<ffffffff80533db6>] device_initial_probe+0xe/0x16
> [<ffffffff80532722>] bus_probe_device+0x86/0x88
> [<ffffffff80532b86>] deferred_probe_work_func+0x70/0xa6
> [<ffffffff800238c2>] process_one_work+0x14a/0x23a
> [<ffffffff80024760>] worker_thread+0x314/0x450
> [<ffffffff8002be5a>] kthread+0x9a/0xae
> [<ffffffff8000248a>] ret_from_fork+0xa/0x1c
> Code: 97ba 000f 0140 4398 000f 08a0 9bbb 0179 ebb3 00eb (a023) 0177
> ---[ end trace 0000000000000000 ]---
> 
> 
>> +        #interrupt-cells = <1>;
>> +
>> +        regulators {
>> +            vdd_cpu: dcdc2 {
>> +                regulator-always-on;
>> +                regulator-min-microvolt = <500000>;
>> +                regulator-max-microvolt = <1540000>;
>> +                regulator-name = "vdd-cpu";
>> +            };
>> +        };
>> +    };
>>   };
>>   &i2c6 {
>>
> 
> Bo

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[PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Mason Huo]

Add the compatible strings for supporting the generic
cpufreq driver on the StarFive JH7110 SoC.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 338cf6cc6596..14aa8281c7f4 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -85,6 +85,8 @@ static const struct of_device_id allowlist[] __initconst = {
 	{ .compatible = "st-ericsson,u9500", },
 	{ .compatible = "st-ericsson,u9540", },
 
+	{ .compatible = "starfive,jh7110", },
+
 	{ .compatible = "ti,omap2", },
 	{ .compatible = "ti,omap4", },
 	{ .compatible = "ti,omap5", },
-- 
2.39.2

Re: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Viresh Kumar]

On 06-06-23, 18:56, Mason Huo wrote:
> Add the compatible strings for supporting the generic
> cpufreq driver on the StarFive JH7110 SoC.
> 
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 338cf6cc6596..14aa8281c7f4 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -85,6 +85,8 @@ static const struct of_device_id allowlist[] __initconst = {
>  	{ .compatible = "st-ericsson,u9500", },
>  	{ .compatible = "st-ericsson,u9540", },
>  
> +	{ .compatible = "starfive,jh7110", },
> +
>  	{ .compatible = "ti,omap2", },
>  	{ .compatible = "ti,omap4", },
>  	{ .compatible = "ti,omap5", },

I thought I already merged it ?

-- 
viresh

Re: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1087 bytes --]

On Tue, Jun 06, 2023 at 04:38:04PM +0530, Viresh Kumar wrote:
> On 06-06-23, 18:56, Mason Huo wrote:
> > Add the compatible strings for supporting the generic
> > cpufreq driver on the StarFive JH7110 SoC.
> > 
> > Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> > ---
> >  drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> > index 338cf6cc6596..14aa8281c7f4 100644
> > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > @@ -85,6 +85,8 @@ static const struct of_device_id allowlist[] __initconst = {
> >  	{ .compatible = "st-ericsson,u9500", },
> >  	{ .compatible = "st-ericsson,u9540", },
> >  
> > +	{ .compatible = "starfive,jh7110", },
> > +
> >  	{ .compatible = "ti,omap2", },
> >  	{ .compatible = "ti,omap4", },
> >  	{ .compatible = "ti,omap5", },
> 
> I thought I already merged it ?

You did, 4b4c0d37164c ("cpufreq: dt-platdev: Add JH7110 SOC to the
allowlist").

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Re: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Mason Huo]

Hi Viresh & Conor,

Sorry for the confusion. 
Should I re-send the patch series and remove this patch?
Or you can just ignore it?

Thanks
Mason

> On Tue, Jun 06, 2023 at 04:38:04PM +0530, Viresh Kumar wrote:
> > On 06-06-23, 18:56, Mason Huo wrote:
> > > Add the compatible strings for supporting the generic cpufreq driver 
> > > on the StarFive JH7110 SoC.
> > > 
> > > Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> > > ---
> > >  drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
> > > b/drivers/cpufreq/cpufreq-dt-platdev.c
> > > index 338cf6cc6596..14aa8281c7f4 100644
> > > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > > @@ -85,6 +85,8 @@ static const struct of_device_id allowlist[] __initconst = {
> > >  	{ .compatible = "st-ericsson,u9500", },
> > >  	{ .compatible = "st-ericsson,u9540", },
> > >  
> > > +	{ .compatible = "starfive,jh7110", },
> > > +
> > >  	{ .compatible = "ti,omap2", },
> > >  	{ .compatible = "ti,omap4", },
> > >  	{ .compatible = "ti,omap5", },
> > 
> > I thought I already merged it ?
> 
> You did, 4b4c0d37164c ("cpufreq: dt-platdev: Add JH7110 SOC to the allowlist").

Re: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Viresh Kumar]

On 07-06-23, 02:04, Mason Huo wrote:
> Or you can just ignore it?

I can do that :)

-- 
viresh

Re: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Conor Dooley]

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On Wed, Jun 07, 2023 at 02:04:37AM +0000, Mason Huo wrote:
> Hi Viresh & Conor,
> 
> Sorry for the confusion. 
> Should I re-send the patch series and remove this patch?
> Or you can just ignore it?

I applied the two dts patches yesterday, you shouldn't need to do
anything.

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Re: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist

[Mason Huo]

Hi Conor & Viresh,

> On Wed, Jun 07, 2023 at 02:04:37AM +0000, Mason Huo wrote:
> > Hi Viresh & Conor,
> > 
> > Sorry for the confusion. 
> > Should I re-send the patch series and remove this patch?
> > Or you can just ignore it?
> 
> I applied the two dts patches yesterday, you shouldn't need to do anything.

Thank you for your help & review.

B.R
Mason

[PATCH v4 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC

[Mason Huo]

Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2.dtsi         | 16 +++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 33 +++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 9714da5550d7..fa0061eb33a7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -230,3 +230,19 @@ &uart0 {
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&U74_1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+	cpu-supply = <&vdd_cpu>;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7eef88d2cedb 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,9 @@ U74_1: cpu@1 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
+			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+			clock-names = "cpu";
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -79,6 +82,9 @@ U74_2: cpu@2 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
+			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+			clock-names = "cpu";
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -105,6 +111,9 @@ U74_3: cpu@3 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
+			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+			clock-names = "cpu";
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -131,6 +140,9 @@ U74_4: cpu@4 {
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			tlb-split;
+			operating-points-v2 = <&cpu_opp>;
+			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+			clock-names = "cpu";
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
@@ -164,6 +176,27 @@ core4 {
 		};
 	};
 
+	cpu_opp: opp-table-0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+			opp-375000000 {
+					opp-hz = /bits/ 64 <375000000>;
+					opp-microvolt = <800000>;
+			};
+			opp-500000000 {
+					opp-hz = /bits/ 64 <500000000>;
+					opp-microvolt = <800000>;
+			};
+			opp-750000000 {
+					opp-hz = /bits/ 64 <750000000>;
+					opp-microvolt = <800000>;
+			};
+			opp-1500000000 {
+					opp-hz = /bits/ 64 <1500000000>;
+					opp-microvolt = <1040000>;
+			};
+	};
+
 	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 		compatible = "fixed-clock";
 		clock-output-names = "gmac0_rgmii_rxin";
-- 
2.39.2

Re: [PATCH v4 0/3] Add JH7110 cpufreq support

[Shengyu Qu]

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Hello,

AXP15060 series just got merged, just to remind this for anyone who 
wants to test this series.

Best regards,
Shengyu

> The StarFive JH7110 SoC has four RISC-V cores,
> and it supports up to 4 cpu frequency loads.
>
> This patchset adds the compatible strings into the allowlist
> for supporting the generic cpufreq driver on JH7110 SoC.
> Also, it enables the axp15060 pmic for the cpu power source.
>
> The series has been tested on the VisionFive 2 boards which
> are equipped with JH7110 SoC and axp15060 pmic.
>
> ---
> This patchset is based on v6.4-rc4 with these patches applied:
> [1] ("regulator: Add X-Powers AXP15060/AXP313a PMIC support")
>      https://lore.kernel.org/lkml/20230524000012.15028-1-andre.przywara@arm.com/
>
> Changes since v3:
> - Fix the dtb_check issues for axp15060 pmic dts configuration.
>
> Changes since v2:
> - Fix the new blank line at EOF issue in dtsi.
>
> Changes since v1:
> - Fix dts node naming issues.
> - Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
> - Follow the alphabetical order to place the cpufreq dt allowlist.
>
> Mason Huo (3):
>    riscv: dts: starfive: Enable axp15060 pmic for cpufreq
>    cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
>    riscv: dts: starfive: Add cpu scaling for JH7110 SoC
>
>   .../jh7110-starfive-visionfive-2.dtsi         | 33 +++++++++++++++++++
>   arch/riscv/boot/dts/starfive/jh7110.dtsi      | 33 +++++++++++++++++++
>   drivers/cpufreq/cpufreq-dt-platdev.c          |  2 ++
>   3 files changed, 68 insertions(+)
>

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