[PATCH 0/3] arm64: qcom: SA8775p: Add llcc support

[PATCH 0/3] arm64: qcom: SA8775p: Add llcc support

[Tengfei Fan]

The SA8775p platform has LLCC as the system cache controller. It
includes 6 LLCC instances and 1 broadcast interface.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---

Tengfei Fan (3):
  dt-bindings: cache: qcom,llcc: Add SA8775p description
  soc: qcom: llcc: Add llcc configuration support for the SA8775p
    platform
  arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platform

 .../devicetree/bindings/cache/qcom,llcc.yaml  | 28 +++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 19 ++++++++++
 drivers/soc/qcom/llcc-qcom.c                  | 35 +++++++++++++++++++
 3 files changed, 82 insertions(+)


base-commit: 9d99040b1bc8dbf385a8aa535e9efcdf94466e19
-- 
2.25.1

[PATCH 1/3] dt-bindings: cache: qcom,llcc: Add SA8775p description

[Tengfei Fan]

Add the cache controller compatible and register region descriptions for
SA8775p platform.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 .../devicetree/bindings/cache/qcom,llcc.yaml  | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 07ccbda4a0ab..37eada55e0f0 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -21,6 +21,7 @@ properties:
   compatible:
     enum:
       - qcom,qdu1000-llcc
+      - qcom,sa8775p-llcc
       - qcom,sc7180-llcc
       - qcom,sc7280-llcc
       - qcom,sc8180x-llcc
@@ -80,6 +81,33 @@ allOf:
             - const: llcc0_base
             - const: llcc_broadcast_base
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sa8775p-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC1 base register region
+            - description: LLCC2 base register region
+            - description: LLCC3 base register region
+            - description: LLCC4 base register region
+            - description: LLCC5 base register region
+            - description: LLCC broadcast base register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc1_base
+            - const: llcc2_base
+            - const: llcc3_base
+            - const: llcc4_base
+            - const: llcc5_base
+            - const: llcc_broadcast_base
+
   - if:
       properties:
         compatible:
-- 
2.25.1

Re: [PATCH 1/3] dt-bindings: cache: qcom,llcc: Add SA8775p description

[Krzysztof Kozlowski]

On 29/05/2024 12:15, Tengfei Fan wrote:
> Add the cache controller compatible and register region descriptions for
> SA8775p platform.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 2/3] soc: qcom: llcc: Add llcc configuration support for the SA8775p platform

[Tengfei Fan]

Add llcc configuration support for the SA8775p platform.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index cbef0dea1d5d..4379a5f8ddf3 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -150,6 +150,25 @@ enum llcc_reg_offset {
 	LLCC_COMMON_STATUS0,
 };
 
+static const struct llcc_slice_config sa8775p_data[] =  {
+	{LLCC_CPUSS,    1, 2048, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 1, 0, 0},
+	{LLCC_VIDSC0,   2, 512, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_CPUSS1,   3, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_CPUHWT,   5, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_AUDIO,    6, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0},
+	{LLCC_CMPT,     10, 4096, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_GPUHTW,   11, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_GPU,      12, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 1, 0},
+	{LLCC_MMUHWT,   13, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0},
+	{LLCC_CMPTDMA,  15, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_DISP,     16, 4096, 2, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_VIDFW,    17, 3072, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_AUDHW,    22, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0},
+	{LLCC_CVP,      28, 256, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
+	{LLCC_APTCM,    30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0},
+	{LLCC_WRCACHE,    31, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0},
+};
+
 static const struct llcc_slice_config sc7180_data[] =  {
 	{ LLCC_CPUSS,    1,  256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
 	{ LLCC_MDM,      8,  128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
@@ -552,6 +571,16 @@ static const struct qcom_llcc_config qdu1000_cfg[] = {
 	},
 };
 
+static const struct qcom_llcc_config sa8775p_cfg[] = {
+	{
+		.sct_data	= sa8775p_data,
+		.size		= ARRAY_SIZE(sa8775p_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+};
+
 static const struct qcom_llcc_config sc7180_cfg[] = {
 	{
 		.sct_data	= sc7180_data,
@@ -698,6 +727,11 @@ static const struct qcom_sct_config qdu1000_cfgs = {
 	.num_config	= ARRAY_SIZE(qdu1000_cfg),
 };
 
+static const struct qcom_sct_config sa8775p_cfgs = {
+	.llcc_config	= sa8775p_cfg,
+	.num_config	= ARRAY_SIZE(sa8775p_cfg),
+};
+
 static const struct qcom_sct_config sc7180_cfgs = {
 	.llcc_config	= sc7180_cfg,
 	.num_config	= ARRAY_SIZE(sc7180_cfg),
@@ -1332,6 +1366,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 
 static const struct of_device_id qcom_llcc_of_match[] = {
 	{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
+	{ .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs },
 	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
 	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
 	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
-- 
2.25.1

[PATCH 3/3] arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platform

[Tengfei Fan]

Add llcc support for the SA8775p platform.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 5632fa896b93..8f910ab113f5 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2885,6 +2885,25 @@ serdes1: phy@8902000 {
 			status = "disabled";
 		};
 
+		llcc: system-cache-controller@9200000 {
+			compatible = "qcom,sa8775p-llcc";
+			reg = <0x0 0x09200000 0x0 0x80000>,
+			      <0x0 0x09300000 0x0 0x80000>,
+			      <0x0 0x09400000 0x0 0x80000>,
+			      <0x0 0x09500000 0x0 0x80000>,
+			      <0x0 0x09600000 0x0 0x80000>,
+			      <0x0 0x09700000 0x0 0x80000>,
+			      <0x0 0x09a00000 0x0 0x80000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc2_base",
+				    "llcc3_base",
+				    "llcc4_base",
+				    "llcc5_base",
+				    "llcc_broadcast_base";
+			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,
-- 
2.25.1

Re: (subset) [PATCH 0/3] arm64: qcom: SA8775p: Add llcc support

[Bjorn Andersson]

On Wed, 29 May 2024 18:15:31 +0800, Tengfei Fan wrote:
> The SA8775p platform has LLCC as the system cache controller. It
> includes 6 LLCC instances and 1 broadcast interface.
> 
> 

Applied, thanks!

[3/3] arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platform
      commit: 809c20b1ffc80200bfcbbeceb0d946a3e0eed3a4

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: (subset) [PATCH 0/3] arm64: qcom: SA8775p: Add llcc support

[Rob Herring]

On Wed, May 29, 2024 at 10:27:00PM -0500, Bjorn Andersson wrote:
> 
> On Wed, 29 May 2024 18:15:31 +0800, Tengfei Fan wrote:
> > The SA8775p platform has LLCC as the system cache controller. It
> > includes 6 LLCC instances and 1 broadcast interface.
> > 
> > 
> 
> Applied, thanks!
> 
> [3/3] arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platform
>       commit: 809c20b1ffc80200bfcbbeceb0d946a3e0eed3a4

I'm confused why you didn't pick up the driver and binding?

Rob

Re: (subset) [PATCH 0/3] arm64: qcom: SA8775p: Add llcc support

[Konrad Dybcio]

On 31.05.2024 3:41 AM, Rob Herring wrote:
> On Wed, May 29, 2024 at 10:27:00PM -0500, Bjorn Andersson wrote:
>>
>> On Wed, 29 May 2024 18:15:31 +0800, Tengfei Fan wrote:
>>> The SA8775p platform has LLCC as the system cache controller. It
>>> includes 6 LLCC instances and 1 broadcast interface.
>>>
>>>
>>
>> Applied, thanks!
>>
>> [3/3] arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platform
>>       commit: 809c20b1ffc80200bfcbbeceb0d946a3e0eed3a4
> 
> I'm confused why you didn't pick up the driver and binding?

He did, although to a different tree (qcom/arm64-for-x.y vs qcom/drivers-for-x.y)

Konrad