[PATCH 0/3] Devicetree updates for MT8186

[PATCH 0/3] Devicetree updates for MT8186

[Rohit Agarwal]

Hi,

This series updates the DPI node to add power domain and
adds the Mediatek SVS node as well to MT8186.

Thanks,
Rohit.

Rohit Agarwal (3):
  dt-bindings: display: mediatek: dpi: Add power domains
  arm64: dts: mediatek: mt8186: Add power domain for DPI
  arm64: dts: mediatek: mt8186: Add svs node

 .../display/mediatek/mediatek,dpi.yaml        |  3 +++
 arch/arm64/boot/dts/mediatek/mt8186.dtsi      | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

-- 
2.46.0.295.g3b9ea8a38a-goog

[PATCH 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Rohit Agarwal]

Add power domain binding to the mediatek DPI controller.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml     | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 5ca7679d5427..10b8572dd922 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -62,6 +62,9 @@ properties:
       - const: default
       - const: sleep
 
+  power-domains:
+    maxItems: 1
+
   port:
     $ref: /schemas/graph.yaml#/properties/port
     description:
-- 
2.46.0.295.g3b9ea8a38a-goog

Re: [PATCH 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Krzysztof Kozlowski]

On Tue, Aug 20, 2024 at 08:06:57AM +0000, Rohit Agarwal wrote:
> Add power domain binding to the mediatek DPI controller.

Why? Who needs it? Why all devices suddenly have it (IOW, why is it not
constrained anyhow per variant)?

> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml     | 3 +++
>  1 file changed, 3 insertions(+)

Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Rohit Agarwal]

On 20/08/24 4:40 PM, Krzysztof Kozlowski wrote:
> On Tue, Aug 20, 2024 at 08:06:57AM +0000, Rohit Agarwal wrote:
>> Add power domain binding to the mediatek DPI controller.
> Why? Who needs it? Why all devices suddenly have it (IOW, why is it not
> constrained anyhow per variant)?
>
Ok, my intent was to introduce only for this particular variant.
Let me constrain it to this particular compatible.

Thanks,
Rohit.
>> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
>> ---
>>   .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml     | 3 +++
>>   1 file changed, 3 insertions(+)
> Best regards,
> Krzysztof
>

Re: [PATCH 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Krzysztof Kozlowski]

On 20/08/2024 14:18, Rohit Agarwal wrote:
> 
> On 20/08/24 4:40 PM, Krzysztof Kozlowski wrote:
>> On Tue, Aug 20, 2024 at 08:06:57AM +0000, Rohit Agarwal wrote:
>>> Add power domain binding to the mediatek DPI controller.
>> Why? Who needs it? Why all devices suddenly have it (IOW, why is it not
>> constrained anyhow per variant)?
>>
> Ok, my intent was to introduce only for this particular variant.
> Let me constrain it to this particular compatible.

Then add property in top-level properties and in if:then: disallow it
for older devices.

Best regards,
Krzysztof

[PATCH 2/3] arm64: dts: mediatek: mt8186: Add power domain for DPI

[Rohit Agarwal]

Add power domain phandle to the DPI controller in mediatek
mt8186 SoC.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 4763ed5dc86c..e27c69ec8bdd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1824,6 +1824,7 @@ dpi: dpi@1400a000 {
 			assigned-clocks = <&topckgen CLK_TOP_DPI>;
 			assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
 			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
+			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
 			status = "disabled";
 
 			port {
-- 
2.46.0.295.g3b9ea8a38a-goog

[PATCH 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Rohit Agarwal]

Add clock/irq/efuse setting in svs nodes for mt8186 SoC.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index e27c69ec8bdd..a51f3d8ce745 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1361,6 +1361,18 @@ spi0: spi@1100a000 {
 			status = "disabled";
 		};
 
+		svs: svs@1100b000 {
+			compatible = "mediatek,mt8186-svs";
+			reg = <0 0x1100b000 0 0x400>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+			clock-names = "main";
+			nvmem-cells = <&svs_calibration>, <&lvts_e_data1>;
+			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+			resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>;
+			reset-names = "svs_rst";
+		};
+
 		pwm0: pwm@1100e000 {
 			compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
 			reg = <0 0x1100e000 0 0x1000>;
@@ -1676,6 +1688,14 @@ efuse: efuse@11cb0000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lvts_e_data1: data@1cc {
+				reg = <0x1cc 0x14>;
+			};
+
+			svs_calibration: calib@550 {
+				reg = <0x550 0x50>;
+			};
+
 			gpu_speedbin: gpu-speedbin@59c {
 				reg = <0x59c 0x4>;
 				bits = <0 3>;
-- 
2.46.0.295.g3b9ea8a38a-goog