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Thu, 13 Nov 2025 07:24:42 -0800 (PST) Message-ID: Date: Thu, 13 Nov 2025 17:24:40 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang References: <20251029133653.2437024-1-claudiu.beznea.uj@bp.renesas.com> <20251029133653.2437024-3-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <20251029133653.2437024-3-claudiu.beznea.uj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, On 10/29/25 15:36, Claudiu wrote: > From: Claudiu Beznea > > The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express > Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions > only as a root complex, with a single-lane (x1) configuration. The > controller includes Type 1 configuration registers, as well as IP > specific registers (called AXI registers) required for various adjustments. > > Hardware manual can be downloaded from the address in the "Link" section. > The following steps should be followed to access the manual: > 1/ Click the "User Manual" button > 2/ Click "Confirm"; this will start downloading an archive > 3/ Open the downloaded archive > 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables > 5/ Open the file r01uh1014ej*-rzg3s.pdf > > Link: https://www.renesas.com/en/products/rz-g3s? > queryID=695cc067c2d89e3f271d43656ede4d12 > Tested-by: Wolfram Sang > Signed-off-by: Claudiu Beznea > --- > > Changes in v6: > - split the help message from Kconfig to 80 chars > - dropped unused defines > - dropped dot at the end of short comments > - re-arranged the members of rzg3s_pcie_child_prepare_bus(), > rzg3s_pcie_child_read_conf(), rzg3s_pcie_child_write_conf(), > rzg3s_pcie_root_map_bus() to save few lines > - in rzg3s_pcie_irq_compose_msi_msg() drop drop_mask and use > RZG3S_PCI_MSIRCVWADRL_MASK > - merge INTx and MSI configuration in rzg3s_pcie_init_irqdomain(); with it, > rzg3s_pcie_host_setup() takes now only 2 function pointer for IRQ domain > config and teardown; also, updated the names of other functions to match > the most used pattern accross other drivers: > -- rzg3s_pcie_msi_enable() -> rzg3s_pcie_init_msi() > -- rzg3s_pcie_host_parse_root_port() -> rzg3s_pcie_host_parse_port() > -- rzg3s_pcie_host_init_root_port() -> rzg3s_pcie_host_init_port() > - used dev_fwnode() instead of of_fwnode_handle() > - used fsleep() instead of usleep_range() > - pass "size - 1" to rzg3s_pcie_set_inbound_window() only and keep the > undecremented value in the calling function > - added a comment on top of request_irq() to explain why devm_ variant > was not used Could you please let me know if there's anything I should be doing for this version? Thank you, Claudiu