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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: pBkLXkv8gaBfMCUCZjs2iIOvP4rh5FeF X-Proofpoint-GUID: pBkLXkv8gaBfMCUCZjs2iIOvP4rh5FeF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE4MDA3NSBTYWx0ZWRfX19TvcWlO7g29 +xLmVP0gHjlK9WOjhuVUSoSkIwivpqHbl5tCXzNpV3LpUAX2WrYhUI/TgehPQxb0SRPcWwOC2ns pFtY7tuvR1/qXrqjUKVEw3wkKEGjLsJzi8plNvygx7IYe72DedNMgULTAQ8HAo1H9g1VXHxCEqT YwE02zuHhHUc4t5hHky5+M30GUDydFr4HI/k6Uxf1myDryGVhqkM2782aI5ovvnfRvvRyBC7PpH zgJpGmVUruATA4Qq1pGWI3JucErp3q0c7f3x43apcAPvl9sLXX/RdKx/VfguAlrzpgFjCWPYo7x GuVMGXZBQCaCU9mV9HXwQ+jGQvhHvo7mQecZlSPewSs1VDOXCB2yXvvLc8elQWr3URzHErJukU+ CyTxu9RdDxoq94IoEaV9ht4QmQm3G0fuwjlTavEGBzvYrB81jtLvCa37SwSjChQP8w8GeqCvIUE 5hLPUMZ5Ik21t0gxWww== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE4MDA3NSBTYWx0ZWRfX83fqLU1TS3SI Xw3PaQQclzrWgr+lITjow4WEkJqRPBq/KOCvN28s92hiw2HtVXOVJtr0qEhjokZoE0UOlYjbrED YZGSEeFDqB1WVEfaEBZcZqo4k8TKxfU= X-Authority-Analysis: v=2.4 cv=YJKvDxGx c=1 sm=1 tr=0 ts=6a33aa0c cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=ZhBa3tV6RTI7cPQeaSoA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-18_01,2026-06-17_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606180075 On 6/16/26 11:25 AM, Maulik Shah wrote: > All PDC irqchip supports pass through mode in which both Direct SPIs and > GPIO IRQs (as SPIs) are sent to GIC without latching at PDC. > > Newer PDCs (v3.0 onwards) also support additional secondary controller mode > where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs > still works same as pass through mode without latching at PDC even in > secondary controller mode. > > All the SoCs so far default uses pass through mode with the exception of > x1e. x1e PDC may be set to secondary controller mode for builds on CRD > boards whereas it may be set to pass through mode for IoT-EVK boards. > The mode configuration is done in firmware and initially shipped windows > firmware did not have SCM interface to read or modify the PDC mode. > Later only write access is opened up for non secure world. > > Using the write access available add changes to modify the PDC mode to > pass through mode via SCM write. When the write fails (on older firmware) > assume to work in secondary mode. > > In secondary mode set the separate irqchip for the GPIOs to perform > additional operations only for the GPIO irqs. > > Co-developed-by: Sneh Mankad > Signed-off-by: Sneh Mankad > Signed-off-by: Maulik Shah > --- [...] > +static void pdc_clear_gpio_cfg(int pin_out) > +{ > + unsigned long gpio_sts; > + > + if (pdc->version < PDC_VERSION_3_0) > + return; > + > + gpio_sts = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); > + __clear_bit(pdc->cfg_fields->gpio_irq_sts, &gpio_sts); > + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_sts); > +} > + > +static void pdc_unmask_gpio_cfg(int pin_out, bool unmask) > +{ > + unsigned long gpio_mask; > + > + if (pdc->version < PDC_VERSION_3_0) > + return; These version checks should be unnecessary now, given the function pointer is only assigned for hamoa Konrad