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[83.9.1.44]) by smtp.gmail.com with ESMTPSA id w26-20020ac2599a000000b004b40c2fccfdsm474474lfn.59.2022.12.13.10.54.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Dec 2022 10:54:16 -0800 (PST) Message-ID: Date: Tue, 13 Dec 2022 19:54:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm6115: Add USB SS qmp phy node Content-Language: en-US To: Bhupesh Sharma , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, agross@kernel.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, andersson@kernel.org References: <20221213123823.455731-1-bhupesh.sharma@linaro.org> <20221213123823.455731-4-bhupesh.sharma@linaro.org> <39ff2174-6d04-ec21-b762-377ed28088cb@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 13.12.2022 19:52, Bhupesh Sharma wrote: > Hi Krzysztof, > > On Tue, 13 Dec 2022 at 18:26, Krzysztof Kozlowski > wrote: >> >> On 13/12/2022 13:38, Bhupesh Sharma wrote: >>> Add USB superspeed qmp phy node to dtsi. >>> >>> Signed-off-by: Bhupesh Sharma >>> --- >>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 38 ++++++++++++++++++++++++++-- >>> 1 file changed, 36 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>> index e4ce135264f3d..9c5c024919f92 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>> @@ -579,6 +579,40 @@ usb_hsphy: phy@1613000 { >>> status = "disabled"; >>> }; >>> >>> + usb_qmpphy: phy@1615000 { >>> + compatible = "qcom,sm6115-qmp-usb3-phy"; >>> + reg = <0x01615000 0x200>; >>> + #clock-cells = <1>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges; >>> + clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >>> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, >>> + <&gcc GCC_AHB2PHY_USB_CLK>; >>> + clock-names = "com_aux", >>> + "ref", >>> + "cfg_ahb"; >>> + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, >>> + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; >>> + reset-names = "phy", "phy_phy"; >>> + status = "disabled"; >> >> Hm, you add a disabled PHY which is used by existing controller. The >> controller is enabled in board DTS, but new PHY node isn't. Aren't you >> now breaking it? > > The USB controller is connected to two PHYs - one is HS PHY and the other is SS > QMP Phy. So while the exiting board dts describes and uses only the HS > PHY, newer > board dts files (which will soon be sent out as a separate patch), > will use both the HS and SS > USB PHYs. It will break Oneplus billie2, you need to specify just the usb2 phy (and phy-names with just usb2-phy) there. Otherwise it's gonna end up waiting infinitely for the usb3 one to probe (but it won't because it's disabled) Konrad > > So, this will not break the existing board dts files. > >>> + >>> + usb_ssphy: phy@1615200 { >>> + reg = <0x01615200 0x200>, >>> + <0x01615400 0x200>, >>> + <0x01615c00 0x400>, >>> + <0x01615600 0x200>, >>> + <0x01615800 0x200>, >>> + <0x01615a00 0x100>; >>> + #phy-cells = <0>; >>> + #clock-cells = <1>; >>> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >>> + clock-names = "pipe0"; >>> + clock-output-names = "usb3_phy_pipe_clk_src"; >>> + }; >>> + }; >>> + >>> + >> >> Just one blank line. > > Ok, Will fix it in v2. > >>> qfprom@1b40000 { >>> compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; >>> reg = <0x01b40000 0x7000>; >>> @@ -1023,8 +1057,8 @@ usb_dwc3: usb@4e00000 { >>> compatible = "snps,dwc3"; >>> reg = <0x04e00000 0xcd00>; >>> interrupts = ; >>> - phys = <&usb_hsphy>; >>> - phy-names = "usb2-phy"; >>> + phys = <&usb_hsphy>, <&usb_ssphy>; >>> + phy-names = "usb2-phy", "usb3-phy"; >>> iommus = <&apps_smmu 0x120 0x0>; >>> snps,dis_u2_susphy_quirk; >>> snps,dis_enblslpm_quirk; >> > > Thanks, > Bhupesh