Re: [PATCH v4 5/9] spi: Documentation: add page on multi-lane support

[David Lechner <dlechner@baylibre.com>]

On 1/8/26 6:44 AM, Marcelo Schmitt wrote:
> Actually, one more thing ...
> 
> On 12/19, David Lechner wrote:
>> Add a new page to Documentation/spi/ describing how multi-lane SPI
>> support works. This is uncommon functionality so it deserves its own
>> documentation page.
>>
>> Signed-off-by: David Lechner <dlechner@baylibre.com>
>> ---
> ...
>> +- :c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data words
>> +    at the same time, one on each lane. This means that the buffer needs to be
>> +    sized to hold data for all lanes. Data is interleaved in the buffer, with
>> +    the first word corresponding to lane 0, the second to lane 1, and so on.
>> +    Once the last lane is used, the next word in the buffer corresponds to lane
>> +    0 again. Accordingly, the buffer size must be a multiple of the number of
>> +    lanes. This mode works for both reads and writes.
>> +
>> +    Example::
>> +
>> +        struct spi_transfer xfer = {
>> +            .rx_buf = rx_buf,
>> +            .len = 2,
>> +            .multi_lane_mode = SPI_MULTI_BUS_MODE_STRIPE,
>> +        };
>> +
>> +        spi_sync_transfer(spi, &xfer, 1);
>> +
>> +    Each tx wire has a different data word sent simultaneously::
> In this example, the controller is reading data so the rx wires have different
> data word received?

Yes, I tried to make that clear below by having a different value
for each.
> 
>> +
>> +        controller    < data bits <     peripheral
>> +        ----------   ----------------   ----------
>> +            SDI 0    0-0-0-1-0-0-0-1    SDO 0
>> +            SDI 1    1-0-0-0-1-0-0-0    SDO 1
>> +
>> +    After the transfer, ``rx_buf[0] == 0x11`` (word from SDO 0) and
>> +    ``rx_buf[1] == 0x88`` (word from SDO 1).