From: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, weiyi.lu@mediatek.com, ikjn@chromium.org,
chun-jie.chen@mediatek.com, tinghan.shen@mediatek.com,
seiya.wang@mediatek.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH 0/2] MT8192/95: Set correct MSDCPLL rate
Date: Mon, 29 May 2023 18:08:56 +0200 [thread overview]
Message-ID: <cabc40f3-d1cb-bdd0-bd96-1a51cb861579@gmail.com> (raw)
In-Reply-To: <20230522093002.75137-1-angelogioacchino.delregno@collabora.com>
On 22/05/2023 11:30, AngeloGioacchino Del Regno wrote:
> This series improves both stability/reliability and performance for
> eMMC and SD cards on MT8192 and MT8195, where the PLL may be set at
> a sub-optimal rate from the bootloader.
>
> This was tested on MT8192 Asurada Spherion and MT8195 Cherry Tomato
> Chromebooks.
>
> AngeloGioacchino Del Regno (2):
> arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz
> arm64: dts: mediatek: mt8195: Make sure MSDCPLL's rate is 400MHz
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++
> 2 files changed, 4 insertions(+)
>
Whole series applied, thanks a lot!
Matthias
prev parent reply other threads:[~2023-05-29 16:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-22 9:30 [PATCH 0/2] MT8192/95: Set correct MSDCPLL rate AngeloGioacchino Del Regno
2023-05-22 9:30 ` [PATCH 1/2] arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz AngeloGioacchino Del Regno
2023-06-15 9:51 ` TingHan Shen (沈廷翰)
2023-06-15 11:16 ` Matthias Brugger
2023-06-19 7:33 ` AngeloGioacchino Del Regno
2023-05-22 9:30 ` [PATCH 2/2] arm64: dts: mediatek: mt8195: " AngeloGioacchino Del Regno
2023-05-29 16:08 ` Matthias Brugger [this message]
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