[PATCH v5 0/3] Add USB2PHY Port Reset Control driver for Renesas RZ/V2H(P) SoC

[PATCH v5 0/3] Add USB2PHY Port Reset Control driver for Renesas RZ/V2H(P) SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds support for the USB2PHY Port Reset control driver
for the Renesas RZ/V2H(P) SoC. The changes include documenting the USB2PHY
Port Reset control bindings and adding the driver.

v4->v5
- Added Reviewed-by tag from Biju Das for patch 2/3
- Dropped NULL check for of_device_get_match_data() in probe()
- Dropped dev_set_drvdata() in probe()

v3->v4
- Added Reviewed-by tag from Krzysztof Kozlowski for patch 1/3
- Updated commit message for patch 1/3 as per review comments

v2->v3
- Dropped Acks from Conor and Fabrizio, due to below changes
- Renamed binding renesas,rzv2h-usb2phy-ctrl.yaml to
  renesas,rzv2h-usb2phy-reset.yaml
- Renamed node name in example to reset-controller
- Renamed function names in reset-rzv2h-usb2phy.c
- Kept the reset line in asserted state during probe
- Added comment for rzv2h_init_vals[]
- Added entry in MAINTAINERS file

v1->v2
- Dropped binding postfix in subject line for patch 1/2
- Moved acquiring the ctrl2 pin in deassert callback
- Updated ctrl_status_bits

Cheers,
Prabhakar

Lad Prabhakar (3):
  dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
  reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
  MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver

 .../reset/renesas,rzv2h-usb2phy-reset.yaml    |  56 +++++
 MAINTAINERS                                   |   8 +
 drivers/reset/Kconfig                         |   7 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-rzv2h-usb2phy.c           | 236 ++++++++++++++++++
 5 files changed, 308 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
 create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c


base-commit: 5b37f7bfff3b1582c34be8fb23968b226db71ebd
-- 
2.49.0

[PATCH v5 1/3] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset
controller. This block manages the reset and power-down of the USB 2.0 PHY,
which is used in both host and function modes.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../reset/renesas,rzv2h-usb2phy-reset.yaml    | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
new file mode 100644
index 000000000000..c79f61c2373b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H(P) USB2PHY Port reset Control
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description:
+  The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the
+  USB2.0 PHY.
+
+properties:
+  compatible:
+    const: renesas,r9a09g057-usb2phy-reset     # RZ/V2H(P)
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - power-domains
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
+
+    reset-controller@15830000 {
+        compatible = "renesas,r9a09g057-usb2phy-reset";
+        reg = <0x15830000 0x10000>;
+        clocks = <&cpg CPG_MOD 0xb6>;
+        resets = <&cpg 0xaf>;
+        power-domains = <&cpg>;
+        #reset-cells = <0>;
+    };
-- 
2.49.0

[PATCH v5 2/3] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC.
Enable control of USB2.0 PHY reset and power-down operations, including
assert and deassert functionalities for the PHY.

Leverage device tree (OF) data to support future SoCs with similar USB2PHY
hardware but varying register configurations. Define initialization values
and control register settings to ensure flexibility for upcoming platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/reset/Kconfig               |   7 +
 drivers/reset/Makefile              |   1 +
 drivers/reset/reset-rzv2h-usb2phy.c | 236 ++++++++++++++++++++++++++++
 3 files changed, 244 insertions(+)
 create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 11ce86c8156b..d85be5899da6 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -225,6 +225,13 @@ config RESET_RZG2L_USBPHY_CTRL
 	  Support for USBPHY Control found on RZ/G2L family. It mainly
 	  controls reset and power down of the USB/PHY.
 
+config RESET_RZV2H_USB2PHY
+	tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	help
+	  Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
+	  (and similar SoCs).
+
 config RESET_SCMI
 	tristate "Reset driver controlled via ARM SCMI interface"
 	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 6322a191e2a8..91e6348e3351 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
 obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
+obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c
new file mode 100644
index 000000000000..ae643575b067
--- /dev/null
+++ b/drivers/reset/reset-rzv2h-usb2phy.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2H(P) USB2PHY Port reset control driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
+
+struct rzv2h_usb2phy_regval {
+	u16 reg;
+	u16 val;
+};
+
+struct rzv2h_usb2phy_reset_of_data {
+	const struct rzv2h_usb2phy_regval *init_vals;
+	unsigned int init_val_count;
+
+	u16 reset_reg;
+	u16 reset_assert_val;
+	u16 reset_deassert_val;
+	u16 reset_status_bits;
+	u16 reset_release_val;
+
+	u16 reset2_reg;
+	u16 reset2_acquire_val;
+	u16 reset2_release_val;
+};
+
+struct rzv2h_usb2phy_reset_priv {
+	const struct rzv2h_usb2phy_reset_of_data *data;
+	void __iomem *base;
+	struct device *dev;
+	struct reset_controller_dev rcdev;
+	spinlock_t lock; /* protects register accesses */
+};
+
+static inline struct rzv2h_usb2phy_reset_priv
+*rzv2h_usbphy_rcdev_to_priv(struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct rzv2h_usb2phy_reset_priv, rcdev);
+}
+
+/* This function must be called only after pm_runtime_resume_and_get() has been called */
+static void rzv2h_usbphy_assert_helper(struct rzv2h_usb2phy_reset_priv *priv)
+{
+	const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
+
+	scoped_guard(spinlock, &priv->lock) {
+		writel(data->reset2_acquire_val, priv->base + data->reset2_reg);
+		writel(data->reset_assert_val, priv->base + data->reset_reg);
+	}
+
+	usleep_range(11, 20);
+}
+
+static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
+	struct device *dev = priv->dev;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		dev_err(dev, "pm_runtime_resume_and_get failed\n");
+		return ret;
+	}
+
+	rzv2h_usbphy_assert_helper(priv);
+
+	pm_runtime_put(dev);
+
+	return 0;
+}
+
+static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev,
+				       unsigned long id)
+{
+	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
+	const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
+	struct device *dev = priv->dev;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		dev_err(dev, "pm_runtime_resume_and_get failed\n");
+		return ret;
+	}
+
+	scoped_guard(spinlock, &priv->lock) {
+		writel(data->reset_deassert_val, priv->base + data->reset_reg);
+		writel(data->reset2_release_val, priv->base + data->reset2_reg);
+		writel(data->reset_release_val, priv->base + data->reset_reg);
+	}
+
+	pm_runtime_put(dev);
+
+	return 0;
+}
+
+static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
+	struct device *dev = priv->dev;
+	int ret;
+	u32 reg;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		dev_err(dev, "pm_runtime_resume_and_get failed\n");
+		return ret;
+	}
+
+	reg = readl(priv->base + priv->data->reset_reg);
+
+	pm_runtime_put(dev);
+
+	return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits;
+}
+
+static const struct reset_control_ops rzv2h_usbphy_reset_ops = {
+	.assert = rzv2h_usbphy_reset_assert,
+	.deassert = rzv2h_usbphy_reset_deassert,
+	.status = rzv2h_usbphy_reset_status,
+};
+
+static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev,
+					const struct of_phandle_args *reset_spec)
+{
+	/* No special handling needed, we have only one reset line per device */
+	return 0;
+}
+
+static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
+{
+	const struct rzv2h_usb2phy_reset_of_data *data;
+	struct rzv2h_usb2phy_reset_priv *priv;
+	struct device *dev = &pdev->dev;
+	struct reset_control *rstc;
+	int error;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	data = of_device_get_match_data(dev);
+	priv->data = data;
+	priv->dev = dev;
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	rstc = devm_reset_control_get_shared_deasserted(dev, NULL);
+	if (IS_ERR(rstc))
+		return dev_err_probe(dev, PTR_ERR(rstc),
+				     "failed to get deasserted reset\n");
+
+	spin_lock_init(&priv->lock);
+
+	error = devm_pm_runtime_enable(dev);
+	if (error)
+		return dev_err_probe(dev, error, "Failed to enable pm_runtime\n");
+
+	error = pm_runtime_resume_and_get(dev);
+	if (error)
+		return dev_err_probe(dev, error, "pm_runtime_resume_and_get failed\n");
+
+	for (unsigned int i = 0; i < data->init_val_count; i++)
+		writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg);
+
+	/* keep usb2phy in asserted state */
+	rzv2h_usbphy_assert_helper(priv);
+
+	pm_runtime_put(dev);
+
+	priv->rcdev.ops = &rzv2h_usbphy_reset_ops;
+	priv->rcdev.of_reset_n_cells = 0;
+	priv->rcdev.nr_resets = 1;
+	priv->rcdev.of_xlate = rzv2h_usb2phy_reset_of_xlate;
+	priv->rcdev.of_node = dev->of_node;
+	priv->rcdev.dev = dev;
+
+	return devm_reset_controller_register(dev, &priv->rcdev);
+}
+
+/*
+ * initialization values required to prepare the PHY to receive
+ * assert and deassert requests.
+ */
+static const struct rzv2h_usb2phy_regval rzv2h_init_vals[] = {
+	{ .reg = 0xc10, .val = 0x67c },
+	{ .reg = 0xc14, .val = 0x1f },
+	{ .reg = 0x600, .val = 0x909 },
+};
+
+static const struct rzv2h_usb2phy_reset_of_data rzv2h_reset_of_data = {
+	.init_vals = rzv2h_init_vals,
+	.init_val_count = ARRAY_SIZE(rzv2h_init_vals),
+	.reset_reg = 0,
+	.reset_assert_val = 0x206,
+	.reset_status_bits = BIT(2),
+	.reset_deassert_val = 0x200,
+	.reset_release_val = 0x0,
+	.reset2_reg = 0xb04,
+	.reset2_acquire_val = 0x303,
+	.reset2_release_val = 0x3,
+};
+
+static const struct of_device_id rzv2h_usb2phy_reset_of_match[] = {
+	{ .compatible = "renesas,r9a09g057-usb2phy-reset", .data = &rzv2h_reset_of_data },
+	{ /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzv2h_usb2phy_reset_of_match);
+
+static struct platform_driver rzv2h_usb2phy_reset_driver = {
+	.driver = {
+		.name		= "rzv2h_usb2phy_reset",
+		.of_match_table	= rzv2h_usb2phy_reset_of_match,
+	},
+	.probe = rzv2h_usb2phy_reset_probe,
+};
+module_platform_driver(rzv2h_usb2phy_reset_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/V2H(P) USB2PHY Control");
-- 
2.49.0

[PATCH v5 3/3] MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add a new MAINTAINERS entry for the Renesas RZ/V2H(P) USB2PHY Port Reset
driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b5acf50fc6af..a8d8eabf9ecf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20684,6 +20684,14 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml
 F:	drivers/usb/gadget/udc/renesas_usbf.c
 
+RENESAS RZ/V2H(P) USB2PHY PORT RESET DRIVER
+M:	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
+M:	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+L:	linux-renesas-soc@vger.kernel.org
+S:	Supported
+F:	Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
+F:	drivers/reset/reset-rzv2h-usb2phy.c
+
 RENESAS RZ/V2M I2C DRIVER
 M:	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
 L:	linux-i2c@vger.kernel.org
-- 
2.49.0

RE: [PATCH v5 1/3] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset

[Fabrizio Castro]

> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 15 April 2025 20:51
> Subject: [PATCH v5 1/3] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset
> controller. This block manages the reset and power-down of the USB 2.0 PHY,
> which is used in both host and function modes.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

> ---
>  .../reset/renesas,rzv2h-usb2phy-reset.yaml    | 56 +++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
> b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
> new file mode 100644
> index 000000000000..c79f61c2373b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H(P) USB2PHY Port reset Control
> +
> +maintainers:
> +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +description:
> +  The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the
> +  USB2.0 PHY.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g057-usb2phy-reset     # RZ/V2H(P)
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  '#reset-cells':
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +  - power-domains
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
> +
> +    reset-controller@15830000 {
> +        compatible = "renesas,r9a09g057-usb2phy-reset";
> +        reg = <0x15830000 0x10000>;
> +        clocks = <&cpg CPG_MOD 0xb6>;
> +        resets = <&cpg 0xaf>;
> +        power-domains = <&cpg>;
> +        #reset-cells = <0>;
> +    };
> --
> 2.49.0

RE: [PATCH v5 2/3] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)

[Fabrizio Castro]

> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 15 April 2025 20:52
> Subject: [PATCH v5 2/3] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC.
> Enable control of USB2.0 PHY reset and power-down operations, including
> assert and deassert functionalities for the PHY.
> 
> Leverage device tree (OF) data to support future SoCs with similar USB2PHY
> hardware but varying register configurations. Define initialization values
> and control register settings to ensure flexibility for upcoming platforms.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

> ---
>  drivers/reset/Kconfig               |   7 +
>  drivers/reset/Makefile              |   1 +
>  drivers/reset/reset-rzv2h-usb2phy.c | 236 ++++++++++++++++++++++++++++
>  3 files changed, 244 insertions(+)
>  create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c
> 
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 11ce86c8156b..d85be5899da6 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -225,6 +225,13 @@ config RESET_RZG2L_USBPHY_CTRL
>  	  Support for USBPHY Control found on RZ/G2L family. It mainly
>  	  controls reset and power down of the USB/PHY.
> 
> +config RESET_RZV2H_USB2PHY
> +	tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
> +	depends on ARCH_RENESAS || COMPILE_TEST
> +	help
> +	  Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
> +	  (and similar SoCs).
> +
>  config RESET_SCMI
>  	tristate "Reset driver controlled via ARM SCMI interface"
>  	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 6322a191e2a8..91e6348e3351 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>  obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
>  obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
>  obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
> +obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
>  obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
>  obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>  obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c
> new file mode 100644
> index 000000000000..ae643575b067
> --- /dev/null
> +++ b/drivers/reset/reset-rzv2h-usb2phy.c
> @@ -0,0 +1,236 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas RZ/V2H(P) USB2PHY Port reset control driver
> + *
> + * Copyright (C) 2025 Renesas Electronics Corporation
> + */
> +
> +#include <linux/cleanup.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/reset-controller.h>
> +
> +struct rzv2h_usb2phy_regval {
> +	u16 reg;
> +	u16 val;
> +};
> +
> +struct rzv2h_usb2phy_reset_of_data {
> +	const struct rzv2h_usb2phy_regval *init_vals;
> +	unsigned int init_val_count;
> +
> +	u16 reset_reg;
> +	u16 reset_assert_val;
> +	u16 reset_deassert_val;
> +	u16 reset_status_bits;
> +	u16 reset_release_val;
> +
> +	u16 reset2_reg;
> +	u16 reset2_acquire_val;
> +	u16 reset2_release_val;
> +};
> +
> +struct rzv2h_usb2phy_reset_priv {
> +	const struct rzv2h_usb2phy_reset_of_data *data;
> +	void __iomem *base;
> +	struct device *dev;
> +	struct reset_controller_dev rcdev;
> +	spinlock_t lock; /* protects register accesses */
> +};
> +
> +static inline struct rzv2h_usb2phy_reset_priv
> +*rzv2h_usbphy_rcdev_to_priv(struct reset_controller_dev *rcdev)
> +{
> +	return container_of(rcdev, struct rzv2h_usb2phy_reset_priv, rcdev);
> +}
> +
> +/* This function must be called only after pm_runtime_resume_and_get() has been called */
> +static void rzv2h_usbphy_assert_helper(struct rzv2h_usb2phy_reset_priv *priv)
> +{
> +	const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
> +
> +	scoped_guard(spinlock, &priv->lock) {
> +		writel(data->reset2_acquire_val, priv->base + data->reset2_reg);
> +		writel(data->reset_assert_val, priv->base + data->reset_reg);
> +	}
> +
> +	usleep_range(11, 20);
> +}
> +
> +static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev,
> +				     unsigned long id)
> +{
> +	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
> +	struct device *dev = priv->dev;
> +	int ret;
> +
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret) {
> +		dev_err(dev, "pm_runtime_resume_and_get failed\n");
> +		return ret;
> +	}
> +
> +	rzv2h_usbphy_assert_helper(priv);
> +
> +	pm_runtime_put(dev);
> +
> +	return 0;
> +}
> +
> +static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev,
> +				       unsigned long id)
> +{
> +	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
> +	const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
> +	struct device *dev = priv->dev;
> +	int ret;
> +
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret) {
> +		dev_err(dev, "pm_runtime_resume_and_get failed\n");
> +		return ret;
> +	}
> +
> +	scoped_guard(spinlock, &priv->lock) {
> +		writel(data->reset_deassert_val, priv->base + data->reset_reg);
> +		writel(data->reset2_release_val, priv->base + data->reset2_reg);
> +		writel(data->reset_release_val, priv->base + data->reset_reg);
> +	}
> +
> +	pm_runtime_put(dev);
> +
> +	return 0;
> +}
> +
> +static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev,
> +				     unsigned long id)
> +{
> +	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
> +	struct device *dev = priv->dev;
> +	int ret;
> +	u32 reg;
> +
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret) {
> +		dev_err(dev, "pm_runtime_resume_and_get failed\n");
> +		return ret;
> +	}
> +
> +	reg = readl(priv->base + priv->data->reset_reg);
> +
> +	pm_runtime_put(dev);
> +
> +	return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits;
> +}
> +
> +static const struct reset_control_ops rzv2h_usbphy_reset_ops = {
> +	.assert = rzv2h_usbphy_reset_assert,
> +	.deassert = rzv2h_usbphy_reset_deassert,
> +	.status = rzv2h_usbphy_reset_status,
> +};
> +
> +static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev,
> +					const struct of_phandle_args *reset_spec)
> +{
> +	/* No special handling needed, we have only one reset line per device */
> +	return 0;
> +}
> +
> +static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
> +{
> +	const struct rzv2h_usb2phy_reset_of_data *data;
> +	struct rzv2h_usb2phy_reset_priv *priv;
> +	struct device *dev = &pdev->dev;
> +	struct reset_control *rstc;
> +	int error;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	data = of_device_get_match_data(dev);
> +	priv->data = data;
> +	priv->dev = dev;
> +	priv->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	rstc = devm_reset_control_get_shared_deasserted(dev, NULL);
> +	if (IS_ERR(rstc))
> +		return dev_err_probe(dev, PTR_ERR(rstc),
> +				     "failed to get deasserted reset\n");
> +
> +	spin_lock_init(&priv->lock);
> +
> +	error = devm_pm_runtime_enable(dev);
> +	if (error)
> +		return dev_err_probe(dev, error, "Failed to enable pm_runtime\n");
> +
> +	error = pm_runtime_resume_and_get(dev);
> +	if (error)
> +		return dev_err_probe(dev, error, "pm_runtime_resume_and_get failed\n");
> +
> +	for (unsigned int i = 0; i < data->init_val_count; i++)
> +		writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg);
> +
> +	/* keep usb2phy in asserted state */
> +	rzv2h_usbphy_assert_helper(priv);
> +
> +	pm_runtime_put(dev);
> +
> +	priv->rcdev.ops = &rzv2h_usbphy_reset_ops;
> +	priv->rcdev.of_reset_n_cells = 0;
> +	priv->rcdev.nr_resets = 1;
> +	priv->rcdev.of_xlate = rzv2h_usb2phy_reset_of_xlate;
> +	priv->rcdev.of_node = dev->of_node;
> +	priv->rcdev.dev = dev;
> +
> +	return devm_reset_controller_register(dev, &priv->rcdev);
> +}
> +
> +/*
> + * initialization values required to prepare the PHY to receive
> + * assert and deassert requests.
> + */
> +static const struct rzv2h_usb2phy_regval rzv2h_init_vals[] = {
> +	{ .reg = 0xc10, .val = 0x67c },
> +	{ .reg = 0xc14, .val = 0x1f },
> +	{ .reg = 0x600, .val = 0x909 },
> +};
> +
> +static const struct rzv2h_usb2phy_reset_of_data rzv2h_reset_of_data = {
> +	.init_vals = rzv2h_init_vals,
> +	.init_val_count = ARRAY_SIZE(rzv2h_init_vals),
> +	.reset_reg = 0,
> +	.reset_assert_val = 0x206,
> +	.reset_status_bits = BIT(2),
> +	.reset_deassert_val = 0x200,
> +	.reset_release_val = 0x0,
> +	.reset2_reg = 0xb04,
> +	.reset2_acquire_val = 0x303,
> +	.reset2_release_val = 0x3,
> +};
> +
> +static const struct of_device_id rzv2h_usb2phy_reset_of_match[] = {
> +	{ .compatible = "renesas,r9a09g057-usb2phy-reset", .data = &rzv2h_reset_of_data },
> +	{ /* Sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, rzv2h_usb2phy_reset_of_match);
> +
> +static struct platform_driver rzv2h_usb2phy_reset_driver = {
> +	.driver = {
> +		.name		= "rzv2h_usb2phy_reset",
> +		.of_match_table	= rzv2h_usb2phy_reset_of_match,
> +	},
> +	.probe = rzv2h_usb2phy_reset_probe,
> +};
> +module_platform_driver(rzv2h_usb2phy_reset_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
> +MODULE_DESCRIPTION("Renesas RZ/V2H(P) USB2PHY Control");
> --
> 2.49.0

RE: [PATCH v5 3/3] MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver

[Fabrizio Castro]

> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 15 April 2025 20:52
> To: Philipp Zabel <p.zabel@pengutronix.de>; Geert Uytterhoeven <geert+renesas@glider.be>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> Magnus Damm <magnus.damm@gmail.com>
> Cc: linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> Prabhakar <prabhakar.csengg@gmail.com>; Biju Das <biju.das.jz@bp.renesas.com>; Fabrizio Castro
> <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH v5 3/3] MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add a new MAINTAINERS entry for the Renesas RZ/V2H(P) USB2PHY Port Reset
> driver.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

> ---
>  MAINTAINERS | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b5acf50fc6af..a8d8eabf9ecf 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20684,6 +20684,14 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml
>  F:	drivers/usb/gadget/udc/renesas_usbf.c
> 
> +RENESAS RZ/V2H(P) USB2PHY PORT RESET DRIVER
> +M:	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> +M:	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +L:	linux-renesas-soc@vger.kernel.org
> +S:	Supported
> +F:	Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
> +F:	drivers/reset/reset-rzv2h-usb2phy.c
> +
>  RENESAS RZ/V2M I2C DRIVER
>  M:	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
>  L:	linux-i2c@vger.kernel.org
> --
> 2.49.0

Re: [PATCH v5 0/3] Add USB2PHY Port Reset Control driver for Renesas RZ/V2H(P) SoC

[Lad, Prabhakar]

Hi Philipp,

On Tue, Apr 15, 2025 at 8:51 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> This patch series adds support for the USB2PHY Port Reset control driver
> for the Renesas RZ/V2H(P) SoC. The changes include documenting the USB2PHY
> Port Reset control bindings and adding the driver.
>
> v4->v5
> - Added Reviewed-by tag from Biju Das for patch 2/3
> - Dropped NULL check for of_device_get_match_data() in probe()
> - Dropped dev_set_drvdata() in probe()
>
> v3->v4
> - Added Reviewed-by tag from Krzysztof Kozlowski for patch 1/3
> - Updated commit message for patch 1/3 as per review comments
>
> v2->v3
> - Dropped Acks from Conor and Fabrizio, due to below changes
> - Renamed binding renesas,rzv2h-usb2phy-ctrl.yaml to
>   renesas,rzv2h-usb2phy-reset.yaml
> - Renamed node name in example to reset-controller
> - Renamed function names in reset-rzv2h-usb2phy.c
> - Kept the reset line in asserted state during probe
> - Added comment for rzv2h_init_vals[]
> - Added entry in MAINTAINERS file
>
> v1->v2
> - Dropped binding postfix in subject line for patch 1/2
> - Moved acquiring the ctrl2 pin in deassert callback
> - Updated ctrl_status_bits
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (3):
>   dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
>   reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
>   MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver
>
>  .../reset/renesas,rzv2h-usb2phy-reset.yaml    |  56 +++++
>  MAINTAINERS                                   |   8 +
>  drivers/reset/Kconfig                         |   7 +
>  drivers/reset/Makefile                        |   1 +
>  drivers/reset/reset-rzv2h-usb2phy.c           | 236 ++++++++++++++++++
>  5 files changed, 308 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
>  create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c
>
Gentle ping for review.

Cheers,
Prabhakar

Re: [PATCH v5 0/3] Add USB2PHY Port Reset Control driver for Renesas RZ/V2H(P) SoC

[Philipp Zabel]

On Di, 2025-04-15 at 20:51 +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This patch series adds support for the USB2PHY Port Reset control driver
> for the Renesas RZ/V2H(P) SoC. The changes include documenting the USB2PHY
> Port Reset control bindings and adding the driver.
> 
> v4->v5
> - Added Reviewed-by tag from Biju Das for patch 2/3
> - Dropped NULL check for of_device_get_match_data() in probe()
> - Dropped dev_set_drvdata() in probe()
[...]

Applied to reset/next, thanks!

[1/3] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=261f3ff29a2b
[2/3] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=e3911d7f865b
[3/3] MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=57dfdfbe1a03

regards
Philipp