From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C422C54EE9 for ; Tue, 13 Sep 2022 07:18:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231152AbiIMHSS (ORCPT ); Tue, 13 Sep 2022 03:18:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230224AbiIMHSR (ORCPT ); Tue, 13 Sep 2022 03:18:17 -0400 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A52BB39BAE; Tue, 13 Sep 2022 00:18:14 -0700 (PDT) Received: from 3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 0AC3B135F; Tue, 13 Sep 2022 09:18:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1663053492; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LXUSM1D9TCSnj5cFkQcurcTTk7FULHs9ic+FItwRGmQ=; b=SV8DHSwgEXZIwRgHNthvy5ZFXif0qMYzsnNw4hWCAC4MSu3ljzH9OugvN/BgIMmJZAeUt3 8/2zwuTxUxupDMlsIWLG1jxc+ruc1DkDxHZN3OqBDw9AIdyRNz5eG8qjMThxbFlotX9UaV ytdTF0e7E6n5364RuY5vAdDjj5Woso4n6Gh4Wg7YqwFFVjlTqL1vPeOBZCiF1CkVeAt0aX YtIFXXhaOBIuwZjDjNRk6b51sXoKGZoa5/7DWqmzvHKCHrpkqS0eNX79sSQcQl0fu9hN0G DICQspqVSKJ3u76ZtAWl19d+YUOrbj34ME7IGnT4UirYduTgpprbV11PXKBfpQ== MIME-Version: 1.0 Date: Tue, 13 Sep 2022 09:18:11 +0200 From: Michael Walle To: Horatiu Vultur Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, claudiu.beznea@microchip.com, nicolas.ferre@microchip.com Subject: Re: [PATCH] ARM: dts: lan966x: Fix the interrupt number for internal PHYs In-Reply-To: <20220912192629.461452-1-horatiu.vultur@microchip.com> References: <20220912192629.461452-1-horatiu.vultur@microchip.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: X-Sender: michael@walle.cc Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Horatiu, Am 2022-09-12 21:26, schrieb Horatiu Vultur: > According to the datasheet the interrupts for internal PHYs are > 80 and 81. Can you point me to that documentation? Accoring to Table 3-155: Shared Peripheral Interrupts There are ID47 and ID48 listed as "MIIM controller 0 interrupt". Whatever that is, because the internal PHYs are on MIIM controller 1. But 80 and 81 would be ID48 and ID49. Did you test the interrupts? -michael > Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes") > Signed-off-by: Horatiu Vultur > --- > arch/arm/boot/dts/lan966x.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/lan966x.dtsi > b/arch/arm/boot/dts/lan966x.dtsi > index bcb130a2471d..23665a042990 100644 > --- a/arch/arm/boot/dts/lan966x.dtsi > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -547,13 +547,13 @@ mdio1: mdio@e200413c { > > phy0: ethernet-phy@1 { > reg = <1>; > - interrupts = ; > + interrupts = ; > status = "disabled"; > }; > > phy1: ethernet-phy@2 { > reg = <2>; > - interrupts = ; > + interrupts = ; > status = "disabled"; > }; > };