* [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs
@ 2025-06-17 10:47 Mihai Sain
2025-06-17 10:47 ` [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Mihai Sain
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Mihai Sain @ 2025-06-17 10:47 UTC (permalink / raw)
To: nicolas.ferre, alexandre.belloni, claudiu.beznea, robh, krzk+dt,
conor+dt, linux-arm-kernel, devicetree, linux-kernel
Cc: Mihai Sain
This patch series adds cache configuration for Microchip SAMA7D and SAMA7G MPUs.
The cache configuration is described in datasheet chapter 15.2.
Mihai Sain (2):
ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
arch/arm/boot/dts/microchip/sama7d65.dtsi | 17 +++++++++++++++++
arch/arm/boot/dts/microchip/sama7g5.dtsi | 17 +++++++++++++++++
2 files changed, 34 insertions(+)
base-commit: 9afe652958c3ee88f24df1e4a97f298afce89407
--
2.49.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node 2025-06-17 10:47 [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Mihai Sain @ 2025-06-17 10:47 ` Mihai Sain 2025-06-17 12:31 ` Nicolas Ferre 2025-06-17 10:47 ` [PATCH 2/2] ARM: dts: microchip: sama7g5: " Mihai Sain 2025-06-17 14:21 ` [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Rob Herring (Arm) 2 siblings, 1 reply; 5+ messages in thread From: Mihai Sain @ 2025-06-17 10:47 UTC (permalink / raw) To: nicolas.ferre, alexandre.belloni, claudiu.beznea, robh, krzk+dt, conor+dt, linux-arm-kernel, devicetree, linux-kernel Cc: Mihai Sain Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch: [ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0 After this patch: [root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l1-cache -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified -r--r--r-- 1 root root 6 Jun 17 11:39 compatible -r--r--r-- 1 root root 4 Jun 17 11:39 d-cache-size -r--r--r-- 1 root root 4 Jun 17 11:39 i-cache-size -r--r--r-- 1 root root 9 Jun 17 11:39 name -r--r--r-- 1 root root 4 Jun 17 11:39 next-level-cache -r--r--r-- 1 root root 4 Jun 17 11:39 phandle [root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l2-cache -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level -r--r--r-- 1 root root 4 Jun 17 11:39 cache-size -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified -r--r--r-- 1 root root 6 Jun 17 11:39 compatible -r--r--r-- 1 root root 9 Jun 17 11:39 name -r--r--r-- 1 root root 4 Jun 17 11:39 phandle Signed-off-by: Mihai Sain <mihai.sain@microchip.com> --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index d08d773b1cc5..951d7af3ad1c 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -32,6 +32,23 @@ cpu0: cpu@0 { device_type = "cpu"; clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; clock-names = "cpu"; + next-level-cache = <&L1>; + + L1: l1-cache { + compatible = "cache"; + cache-level = <1>; + d-cache-size = <32768>; + i-cache-size = <32768>; + cache-unified; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <262144>; + cache-unified; + }; }; }; -- 2.49.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node 2025-06-17 10:47 ` [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Mihai Sain @ 2025-06-17 12:31 ` Nicolas Ferre 0 siblings, 0 replies; 5+ messages in thread From: Nicolas Ferre @ 2025-06-17 12:31 UTC (permalink / raw) To: Mihai Sain, alexandre.belloni, claudiu.beznea, robh, krzk+dt, conor+dt, linux-arm-kernel, devicetree, linux-kernel Mihai, On 17/06/2025 at 12:47, Mihai Sain wrote: > Describe the cache memories according with datasheet chapter 15.2: > - L1 cache configuration with 32KB for both data and instruction cache. > - L2 cache configuration with 256KB unified cache. > > Before this patch: > [ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0 > > After this patch: > [root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l1-cache > -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level > -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified Nope. > -r--r--r-- 1 root root 6 Jun 17 11:39 compatible > -r--r--r-- 1 root root 4 Jun 17 11:39 d-cache-size > -r--r--r-- 1 root root 4 Jun 17 11:39 i-cache-size > -r--r--r-- 1 root root 9 Jun 17 11:39 name > -r--r--r-- 1 root root 4 Jun 17 11:39 next-level-cache > -r--r--r-- 1 root root 4 Jun 17 11:39 phandle > > [root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l2-cache > -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level > -r--r--r-- 1 root root 4 Jun 17 11:39 cache-size > -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified > -r--r--r-- 1 root root 6 Jun 17 11:39 compatible > -r--r--r-- 1 root root 9 Jun 17 11:39 name > -r--r--r-- 1 root root 4 Jun 17 11:39 phandle > > Signed-off-by: Mihai Sain <mihai.sain@microchip.com> > --- > arch/arm/boot/dts/microchip/sama7d65.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi > index d08d773b1cc5..951d7af3ad1c 100644 > --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi > +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi > @@ -32,6 +32,23 @@ cpu0: cpu@0 { > device_type = "cpu"; > clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; > clock-names = "cpu"; > + next-level-cache = <&L1>; > + > + L1: l1-cache { > + compatible = "cache"; > + cache-level = <1>; > + d-cache-size = <32768>; > + i-cache-size = <32768>; > + cache-unified; I don't think unified applied to L1 cache for C-A7. Regards, Nicolas > + next-level-cache = <&L2>; > + }; > + > + L2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <262144>; > + cache-unified; > + }; > }; > }; > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: dts: microchip: sama7g5: Add cache configuration for cpu node 2025-06-17 10:47 [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Mihai Sain 2025-06-17 10:47 ` [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Mihai Sain @ 2025-06-17 10:47 ` Mihai Sain 2025-06-17 14:21 ` [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Rob Herring (Arm) 2 siblings, 0 replies; 5+ messages in thread From: Mihai Sain @ 2025-06-17 10:47 UTC (permalink / raw) To: nicolas.ferre, alexandre.belloni, claudiu.beznea, robh, krzk+dt, conor+dt, linux-arm-kernel, devicetree, linux-kernel Cc: Mihai Sain Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch: [ 0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0 After this patch: [root@sama7g54eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l1-cache -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified -r--r--r-- 1 root root 6 Jun 17 11:39 compatible -r--r--r-- 1 root root 4 Jun 17 11:39 d-cache-size -r--r--r-- 1 root root 4 Jun 17 11:39 i-cache-size -r--r--r-- 1 root root 9 Jun 17 11:39 name -r--r--r-- 1 root root 4 Jun 17 11:39 next-level-cache -r--r--r-- 1 root root 4 Jun 17 11:39 phandle [root@sama7g54eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l2-cache -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level -r--r--r-- 1 root root 4 Jun 17 11:39 cache-size -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified -r--r--r-- 1 root root 6 Jun 17 11:39 compatible -r--r--r-- 1 root root 9 Jun 17 11:39 name -r--r--r-- 1 root root 4 Jun 17 11:39 phandle Signed-off-by: Mihai Sain <mihai.sain@microchip.com> --- arch/arm/boot/dts/microchip/sama7g5.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 17bcdcf0cf4a..70175a35dc3e 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -38,6 +38,23 @@ cpu0: cpu@0 { clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ + next-level-cache = <&L1>; + + L1: l1-cache { + compatible = "cache"; + cache-level = <1>; + d-cache-size = <32768>; + i-cache-size = <32768>; + cache-unified; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <262144>; + cache-unified; + }; }; }; -- 2.49.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs 2025-06-17 10:47 [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Mihai Sain 2025-06-17 10:47 ` [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Mihai Sain 2025-06-17 10:47 ` [PATCH 2/2] ARM: dts: microchip: sama7g5: " Mihai Sain @ 2025-06-17 14:21 ` Rob Herring (Arm) 2 siblings, 0 replies; 5+ messages in thread From: Rob Herring (Arm) @ 2025-06-17 14:21 UTC (permalink / raw) To: Mihai Sain Cc: alexandre.belloni, conor+dt, devicetree, krzk+dt, claudiu.beznea, linux-kernel, nicolas.ferre, linux-arm-kernel On Tue, 17 Jun 2025 13:47:01 +0300, Mihai Sain wrote: > This patch series adds cache configuration for Microchip SAMA7D and SAMA7G MPUs. > The cache configuration is described in datasheet chapter 15.2. > > Mihai Sain (2): > ARM: dts: microchip: sama7d65: Add cache configuration for cpu node > ARM: dts: microchip: sama7g5: Add cache configuration for cpu node > > arch/arm/boot/dts/microchip/sama7d65.dtsi | 17 +++++++++++++++++ > arch/arm/boot/dts/microchip/sama7g5.dtsi | 17 +++++++++++++++++ > 2 files changed, 34 insertions(+) > > > base-commit: 9afe652958c3ee88f24df1e4a97f298afce89407 > -- > 2.49.0 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: using specified base-commit 9afe652958c3ee88f24df1e4a97f298afce89407 If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/microchip/' for 20250617104703.45395-1-mihai.sain@microchip.com: arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): d-cache-size: False schema does not allow 32768 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): i-cache-size: False schema does not allow 32768 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'cache-unified', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected) from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): d-cache-size: False schema does not allow 32768 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): i-cache-size: False schema does not allow 32768 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'cache-unified', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected) from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): d-cache-size: False schema does not allow 32768 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): i-cache-size: False schema does not allow 32768 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2 from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'cache-unified', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected) from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: timer@e0800000 (atmel,sama5d2-tcb): clocks: [[2, 2, 91], [2, 2, 92], [2, 2, 93], [18, 1]] is too long from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: timer@e0800000 (atmel,sama5d2-tcb): clocks: [[2, 2, 91], [2, 2, 92], [2, 2, 93], [17, 1]] is too long from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml# arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: timer@e2814000 (atmel,sama5d2-tcb): clocks: [[2, 2, 88], [2, 2, 89], [2, 2, 90], [18, 1]] is too long from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml# arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: timer@e2814000 (atmel,sama5d2-tcb): clocks: [[2, 2, 88], [2, 2, 89], [2, 2, 90], [17, 1]] is too long from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml# ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-06-17 14:21 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-06-17 10:47 [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Mihai Sain 2025-06-17 10:47 ` [PATCH 1/2] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Mihai Sain 2025-06-17 12:31 ` Nicolas Ferre 2025-06-17 10:47 ` [PATCH 2/2] ARM: dts: microchip: sama7g5: " Mihai Sain 2025-06-17 14:21 ` [PATCH 0/2] Add cache configuration for Microchip SAMA7D and SAMA7G MPUs Rob Herring (Arm)
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