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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org References: <20220801184656.702930-1-matej.vasilevski@seznam.cz> <20220801184656.702930-3-matej.vasilevski@seznam.cz> From: Krzysztof Kozlowski In-Reply-To: <20220801184656.702930-3-matej.vasilevski@seznam.cz> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 01/08/2022 20:46, Matej Vasilevski wrote: > Add second clock phandle to specify the timestamping clock. > You can even use the same clock as the core, or define a fixed-clock > if you need something custom. > > Signed-off-by: Matej Vasilevski > --- > .../bindings/net/can/ctu,ctucanfd.yaml | 23 +++++++++++++++---- > 1 file changed, 19 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > index 4635cb96fc64..90390530f909 100644 > --- a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > +++ b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > @@ -44,9 +44,23 @@ properties: > > clocks: > description: | > - phandle of reference clock (100 MHz is appropriate > - for FPGA implementation on Zynq-7000 system). > - maxItems: 1 > + Phandle of reference clock (100 MHz is appropriate for FPGA > + implementation on Zynq-7000 system). If you wish to use timestamps > + from the controller, add a second phandle with the clock used for > + timestamping. The timestamping clock is optional, if you don't > + add it here, the driver will use the primary clock frequency for > + timestamp calculations. If you need something custom, define > + a fixed-clock oscillator and reference it. This should not be a guide how to write DTS, but description of hardware. The references to driver are also not really appropriate in the bindings (are you 100% sure that all other operating systems and SW have driver which behaves like this...) > + minItems: 1 > + items: > + - description: core clock > + - description: timestamping clock > + > + clock-names: > + minItems: 1 > + items: > + - const: core-clk > + - const: ts-clk > > required: > - compatible > @@ -61,6 +75,7 @@ examples: > ctu_can_fd_0: can@43c30000 { > compatible = "ctu,ctucanfd"; > interrupts = <0 30 4>; > - clocks = <&clkc 15>; > + clocks = <&clkc 15>, <&clkc 16>; > + clock-names = "core-clk", "ts-clk"; > reg = <0x43c30000 0x10000>; > }; Best regards, Krzysztof