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([2a01:e0a:106d:1080:3caf:d840:c911:29a9]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49d26be64a5sm49914055e9.6.2026.09.10.00.13.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Sep 2026 00:13:09 -0700 (PDT) Message-ID: Date: Thu, 10 Sep 2026 09:13:06 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v2 2/4] mmc: meson-gx: enable the bus pipeline clock on T7 To: Lucas Tanure , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260905153234.133217-1-tanure@linux.com> <20260905153234.133217-3-tanure@linux.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260905153234.133217-3-tanure@linux.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/5/26 17:32, Lucas Tanure wrote: > On the T7 SoC, the bus path between the SD/eMMC controllers and the > NIC_MATRIX fabric goes through a pipeline stage inserted by the hardware > design to help timing closure. The stage has its own gate clock and, > when that clock is disabled, a controller that starts a DMA transfer can > never complete it, hanging the storage devices and, from there, the > whole system. > > Add a dedicated match data for the amlogic,t7-mmc compatible that makes > the driver claim and enable the "pipeline" clock for as long as the > device is bound. > > The clock is deliberately not optional: the hardware cannot do DMA > without it, and failing the probe with a clear error is preferable to > booting and hitting an undiagnosable DMA hang later. > > Assisted-by: Claude:claude-fable-5 > Signed-off-by: Lucas Tanure > --- > drivers/mmc/host/meson-gx-mmc.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c > index 694bb443d5f3..c0f1e929fc13 100644 > --- a/drivers/mmc/host/meson-gx-mmc.c > +++ b/drivers/mmc/host/meson-gx-mmc.c > @@ -139,6 +139,7 @@ struct meson_mmc_data { > unsigned int always_on; > unsigned int adjust; > unsigned int irq_sdio_sleep; > + bool has_pipeline_clk; > }; > > struct sd_emmc_desc { > @@ -1204,6 +1205,15 @@ static int meson_mmc_probe(struct platform_device *pdev) > if (IS_ERR(core_clk)) > return PTR_ERR(core_clk); > > + if (host->data->has_pipeline_clk) { > + struct clk *pipe_clk; > + > + pipe_clk = devm_clk_get_enabled(&pdev->dev, "pipeline"); > + if (IS_ERR(pipe_clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(pipe_clk), > + "missing pipeline clock\n"); > + } > + > ret = meson_mmc_clk_init(host); > if (ret) > return ret; > @@ -1322,12 +1332,22 @@ static const struct meson_mmc_data meson_axg_data = { > .irq_sdio_sleep = CLK_V3_IRQ_SDIO_SLEEP, > }; > > +static const struct meson_mmc_data meson_t7_data = { > + .tx_delay_mask = CLK_V3_TX_DELAY_MASK, > + .rx_delay_mask = CLK_V3_RX_DELAY_MASK, > + .always_on = CLK_V3_ALWAYS_ON, > + .adjust = SD_EMMC_V3_ADJUST, > + .irq_sdio_sleep = CLK_V3_IRQ_SDIO_SLEEP, > + .has_pipeline_clk = true, > +}; > + > static const struct of_device_id meson_mmc_of_match[] = { > { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, > { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, > { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, > { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, > { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, > + { .compatible = "amlogic,t7-mmc", .data = &meson_t7_data }, > {} > }; > MODULE_DEVICE_TABLE(of, meson_mmc_of_match); Reviewed-by: Neil Armstrong Thanks, Neil