From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAAD6C10DCE for ; Fri, 6 Mar 2020 09:03:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9EDE62073D for ; Fri, 6 Mar 2020 09:03:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="UWX8JX+x" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726397AbgCFJDp (ORCPT ); Fri, 6 Mar 2020 04:03:45 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:15809 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726025AbgCFJDp (ORCPT ); Fri, 6 Mar 2020 04:03:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 06 Mar 2020 01:02:17 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 06 Mar 2020 01:03:44 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 06 Mar 2020 01:03:44 -0800 Received: from [10.19.64.157] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 6 Mar 2020 09:03:41 +0000 Subject: Re: [PATCH] pwm: tegra: Add support for Tegra194 To: Sandipan Patra , , , , References: <1583407653-30059-1-git-send-email-spatra@nvidia.com> CC: , , , , From: Laxman Dewangan Message-ID: Date: Fri, 6 Mar 2020 14:33:02 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1583407653-30059-1-git-send-email-spatra@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1583485338; bh=vzioGjXD1IUumga+3XM/dUEThHitYjhisxYt6UDi4fk=; h=X-PGP-Universal:Subject:To:References:CC:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding; b=UWX8JX+xbXvTj+Ob23BujOnEyiFtcPUAG7A2WX+W2NmeJxE23xXYhug9LwFbj7DX0 1uwdFYLQLMUtN2vozAEjzRNNql/5hla1B4Ym7glTI+SW5X2ruL3qDnCXUZQcTJainN g1TTOYxPvLv7py8zLLWc0A+NHzA2OnYuCWDkzRXKEDGqYftA7ziHhC0+BhhwsVSokK uof2WppWcN8u3UvSJ7fx5KESnk3pluHEY83HDwCaFOqypL1OE0/k7UG1RYWuJZHSX9 FFnb3ELBac8jsK7xbAOfcfwhL3RjK1jJw25b3npGt3tnWSgSzPqttxlwUd+Fruj6Hi KxB2medoPXObQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thursday 05 March 2020 04:57 PM, Sandipan Patra wrote: > Tegra194 has multiple PWM controllers with each having only one output. > > Also the maxmimum frequency is higher than earlier SoCs. > > Add support for Tegra194 and specify the number of PWM outputs and > maximum supported frequency using device tree match data. > > Signed-off-by: Sandipan Patra > --- > Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 1 + > drivers/pwm/pwm-tegra.c | 6 ++++++ > 2 files changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt > index 0a69ead..74c41e3 100644 > --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt > +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt > @@ -9,6 +9,7 @@ Required properties: > - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 > - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 > - "nvidia,tegra186-pwm": for Tegra186 > + - "nvidia,tegra194-pwm": for Tegra194 > - reg: physical base address and length of the controller's registers > - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of > the cells format. > Acked-by: Laxman Dewangan