[PATCH] arm64: dts: qcom: msm8953: Add uart_5

[PATCH] arm64: dts: qcom: msm8953: Add uart_5

[Luca Weiss]

From: Felix Kaechele <felix@kaechele.ca>

Add the node and pinctrl for uart_5 found on the MSM8953 SoC.

Signed-off-by: Felix Kaechele <felix@kaechele.ca>
[luca: Prepare patch for upstream submission]
Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
---
 arch/arm64/boot/dts/qcom/msm8953.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index af4c341e2533ef2cca593e0dc97003334d3fd6b7..3d6ab83cbce4696a8eb54b16fdb429e191f44637 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -767,6 +767,20 @@ spi_6_sleep: spi-6-sleep-state {
 				bias-disable;
 			};
 
+			uart_5_default: uart-5-default-state {
+				pins = "gpio16", "gpio17", "gpio18", "gpio19";
+				function = "blsp_uart5";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			uart_5_sleep: uart-5-sleep-state {
+				pins = "gpio16", "gpio17", "gpio18", "gpio19";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
 			wcnss_pin_a: wcnss-active-state {
 
 				wcss-wlan2-pins {
@@ -1592,6 +1606,24 @@ blsp2_dma: dma-controller@7ac4000 {
 			qcom,controlled-remotely;
 		};
 
+		uart_5: serial@7aef000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x07aef000 0x200>;
+			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
+			dma-names = "tx", "rx";
+
+			pinctrl-0 = <&uart_5_default>;
+			pinctrl-1 = <&uart_5_sleep>;
+			pinctrl-names = "default", "sleep";
+
+			status = "disabled";
+		};
+
 		i2c_5: i2c@7af5000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			reg = <0x07af5000 0x600>;

---
base-commit: a4cda136f021ad44b8b52286aafd613030a6db5f
change-id: 20250406-msm8953-uart_5-f663eed66041

Best regards,
-- 
Luca Weiss <luca@lucaweiss.eu>

Re: [PATCH] arm64: dts: qcom: msm8953: Add uart_5

[Konrad Dybcio]

On 4/6/25 3:52 PM, Luca Weiss wrote:
> From: Felix Kaechele <felix@kaechele.ca>
> 
> Add the node and pinctrl for uart_5 found on the MSM8953 SoC.
> 
> Signed-off-by: Felix Kaechele <felix@kaechele.ca>
> [luca: Prepare patch for upstream submission]
> Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
> ---
>  arch/arm64/boot/dts/qcom/msm8953.dtsi | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
> index af4c341e2533ef2cca593e0dc97003334d3fd6b7..3d6ab83cbce4696a8eb54b16fdb429e191f44637 100644
> --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
> @@ -767,6 +767,20 @@ spi_6_sleep: spi-6-sleep-state {
>  				bias-disable;
>  			};
>  
> +			uart_5_default: uart-5-default-state {
> +				pins = "gpio16", "gpio17", "gpio18", "gpio19";
> +				function = "blsp_uart5";
> +				drive-strength = <16>;

This guy's strongly biased! But it looks like that's on purpose for
these older SoCs..

> +				bias-disable;
> +			};
> +
> +			uart_5_sleep: uart-5-sleep-state {
> +				pins = "gpio16", "gpio17", "gpio18", "gpio19";
> +				function = "gpio";
> +				drive-strength = <2>;
> +				bias-disable;
> +			};
> +
>  			wcnss_pin_a: wcnss-active-state {
>  
>  				wcss-wlan2-pins {
> @@ -1592,6 +1606,24 @@ blsp2_dma: dma-controller@7ac4000 {
>  			qcom,controlled-remotely;
>  		};
>  
> +		uart_5: serial@7aef000 {
> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0x07aef000 0x200>;
> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
> +				 <&gcc GCC_BLSP2_AHB_CLK>;
> +			clock-names = "core",
> +				      "iface";
> +			dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
> +			dma-names = "tx", "rx";

Matches what the computer says

It's more usual to send these together with a user, but I don't mind

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH] arm64: dts: qcom: msm8953: Add uart_5

[Luca Weiss]

On 4/10/25 6:45 PM, Konrad Dybcio wrote:
> On 4/6/25 3:52 PM, Luca Weiss wrote:
>> From: Felix Kaechele <felix@kaechele.ca>
>>
>> Add the node and pinctrl for uart_5 found on the MSM8953 SoC.
>>
>> Signed-off-by: Felix Kaechele <felix@kaechele.ca>
>> [luca: Prepare patch for upstream submission]
>> Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
>> ---
>>   arch/arm64/boot/dts/qcom/msm8953.dtsi | 32 ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
>> index af4c341e2533ef2cca593e0dc97003334d3fd6b7..3d6ab83cbce4696a8eb54b16fdb429e191f44637 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
>> @@ -767,6 +767,20 @@ spi_6_sleep: spi-6-sleep-state {
>>   				bias-disable;
>>   			};
>>   
>> +			uart_5_default: uart-5-default-state {
>> +				pins = "gpio16", "gpio17", "gpio18", "gpio19";
>> +				function = "blsp_uart5";
>> +				drive-strength = <16>;
> 
> This guy's strongly biased! But it looks like that's on purpose for
> these older SoCs..
> 
>> +				bias-disable;
>> +			};
>> +
>> +			uart_5_sleep: uart-5-sleep-state {
>> +				pins = "gpio16", "gpio17", "gpio18", "gpio19";
>> +				function = "gpio";
>> +				drive-strength = <2>;
>> +				bias-disable;
>> +			};
>> +
>>   			wcnss_pin_a: wcnss-active-state {
>>   
>>   				wcss-wlan2-pins {
>> @@ -1592,6 +1606,24 @@ blsp2_dma: dma-controller@7ac4000 {
>>   			qcom,controlled-remotely;
>>   		};
>>   
>> +		uart_5: serial@7aef000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x07aef000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
>> +				 <&gcc GCC_BLSP2_AHB_CLK>;
>> +			clock-names = "core",
>> +				      "iface";
>> +			dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
>> +			dma-names = "tx", "rx";
> 
> Matches what the computer says
> 
> It's more usual to send these together with a user, but I don't mind

This seems to be used with the out-of-tree dts
apq8053-lenovo-cd-18781y.dts

I'm just sometimes trying to reduce the out-of-tree diff of the
msm8953-mailine tree on GitHub

Regards
Luca

> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Konrad

Re: [PATCH] arm64: dts: qcom: msm8953: Add uart_5

[Konrad Dybcio]

On 4/12/25 10:34 AM, Luca Weiss wrote:
> On 4/10/25 6:45 PM, Konrad Dybcio wrote:
>> On 4/6/25 3:52 PM, Luca Weiss wrote:
>>> From: Felix Kaechele <felix@kaechele.ca>
>>>
>>> Add the node and pinctrl for uart_5 found on the MSM8953 SoC.
>>>
>>> Signed-off-by: Felix Kaechele <felix@kaechele.ca>
>>> [luca: Prepare patch for upstream submission]
>>> Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
>>> ---

[...]

>>
>> It's more usual to send these together with a user, but I don't mind
> 
> This seems to be used with the out-of-tree dts
> apq8053-lenovo-cd-18781y.dts
> 
> I'm just sometimes trying to reduce the out-of-tree diff of the
> msm8953-mailine tree on GitHub

Sure that's fine

Konrad

Re: [PATCH] arm64: dts: qcom: msm8953: Add uart_5

[Bjorn Andersson]

On Sun, 06 Apr 2025 15:52:02 +0200, Luca Weiss wrote:
> Add the node and pinctrl for uart_5 found on the MSM8953 SoC.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: msm8953: Add uart_5
      commit: b7bc69b90736a281490d535c6786b6c23c1b22e8

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>