Re: [PATCH v3 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 18/07/2022 16:24, Ivan Bornyakov wrote:
> On Mon, Jul 18, 2022 at 03:58:22PM +0200, Krzysztof Kozlowski wrote:
>> On 18/07/2022 13:49, Ivan Bornyakov wrote:
>>> Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave
>>> SPI to load .bit formatted uncompressed bitstream image.
>>>
>>> Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
>>> ---
>>>  .../bindings/fpga/lattice,ecp5-fpga-mgr.yaml  | 73 +++++++++++++++++++
>>>  1 file changed, 73 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>>> new file mode 100644
>>> index 000000000000..bb10fd316f94
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>>> @@ -0,0 +1,73 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-fpga-mgr.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Lattice ECP5 Slave SPI FPGA manager.
>>> +
>>> +maintainers:
>>> +  - Ivan Bornyakov <i.bornyakov@metrotek.ru>
>>> +
>>> +description:
>>> +  FPGA Manager capable to program Lattice ECP5 with uncompressed bitstream
>>> +  image in .bit format over SPI.
>>
>> The same question as before - you need to explain what is the hardware
>> (not Linux API or Linux subsystem).
>>
> 
> I really don't know what to say aside from "thing that capable to
> program FPGA". Is there a good exmple of proper wording in
> Documentation/devicetree/bindings/fpga/?
> Otherwise I would ask FPGA Manager framework maintainers assistance on
> how to describe a FPGA Manager driver.

I think my first reply had some leads to possible description. Is it a
piece of FPGA? Is it a programmable block of FPGA? Is it dedicated chip
on SPI line? The only problem I see with description is that word
"manager" is too generic and people can call everything manager...

Best regards,
Krzysztof