Re: [PATCH 3/4] dt-bindings: usb: add CIX Sky1 Cadence USB3 controller

[Krzysztof Kozlowski <krzk@kernel.org>]

On 15/05/2026 12:25, Peter Chen wrote:
> On 26-05-15 09:54:10, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On Mon, May 11, 2026 at 10:42:43AM +0800, Peter Chen wrote:
>>> Add a binding for the CIX Sky1 integration of the Cadence USBSSP DRD
>>> controller. The schema documents the glue register window, clocks,
>>> resets, interrupts and S5 system controller phandle.
>>>
>>> Signed-off-by: Peter Chen <peter.chen@cixtech.com>
>>> ---
>>>  .../bindings/usb/cix,sky1-cdns3.yaml          | 151 ++++++++++++++++++
>>
>> Why are you mixing USB patches with DTS in one patchset? Don't.
> 
> In this series, the 1st patch is the IP core driver changes (export APIs for glue layer
> use), and the second glue layer patch is the user for new adding APIs.


Not really answer to my question. Why is DTS here? It has nothing to do
with 1st patch, second patch or this one.


> Normally, we combine dt-binding, driver (glue layer) and DTS changes at one patch series.
> 
> It is much like below submission:
> 
> https://lore.kernel.org/all/20250318-dwc3-refactor-v5-0-90ea6e5b3ba4@oss.qualcomm.com/

Which is also wrong. Why do people pick bad examples as arguments
instead of finding one of my many emails telling why is that incorrect?
Or maybe all the folks who dig through the archives and found my emails
did not continued discussion...


Best regards,
Krzysztof