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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.2 (3.52.2-1.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-07-08 at 17:05 +0100, Jonathan Cameron wrote: > On Mon, 8 Jul 2024 05:17:55 +0000 > "Tinaco, Mariel" wrote: >=20 > > > -----Original Message----- > > > From: Jonathan Cameron > > > Sent: Saturday, June 29, 2024 2:46 AM > > > To: Tinaco, Mariel > > > Cc: linux-iio@vger.kernel.org; devicetree@vger.kernel.org; linux- > > > kernel@vger.kernel.org; Lars-Peter Clausen ; Rob Her= ring > > > ; Krzysztof Kozlowski ; Conor Do= oley > > > ; Liam Girdwood ; Mark Brow= n > > > ; Hennerich, Michael ; > > > Marcelo Schmitt ; Dimitri Fedrau > > > ; Guenter Roeck > > > Subject: Re: [PATCH 2/2] iio: dac: support the ad8460 Waveform DAC > > >=20 > > > [External] > > > =C2=A0=20 > > > > > > +}; > > > > > > + > > > > > > +static int ad8460_get_powerdown_mode(struct iio_dev *indio_dev= , > > > > > > + =C2=A0=C2=A0=C2=A0=C2=A0 const struct iio_chan_spec *chan)= { > > > > > > + return 0;=C2=A0=20 > > > > >=20 > > > > > Why have the stubs in here?=C2=A0=20 > > > >=20 > > > > Should I move the stubs to a different place in the code or remove > > > > them altogether since there is only a single powerdown mode availab= le=C2=A0=20 > > > Ah. I'd not really understood what was going on here.=C2=A0 This is f= ine as is. > > > =C2=A0=20 > > > > > AD8460_HVDAC_DATA_WORD_HIGH(index),=C2=A0=20 > > > > > > + =C2=A0=C2=A0=C2=A0 ((val >> 8) & 0xFF));=C2=A0=20 > > > > >=20 > > > > > bulk write? or do these need to be ordered?=C2=A0=20 > > > >=20 > > > > For this I used bulk read/write this way. > > > >=20 > > > > static int ad8460_set_hvdac_word(struct ad8460_state *state, > > > > int index, > > > > int val) > > > > { > > > > u8 regvals[AD8460_DATA_BYTE_WORD_LENGTH];=C2=A0=20 > > > regmap bulk accesses (when spi anyway) should be provided with DMA sa= fe > > > buffers. > > > Easiest way to do that is add one with __aligned(IIO_DMA_MINALIGN) to= the > > > end of the ad8460_state structure.=C2=A0 Possibly you'll need a lock = to protect it - > > > I > > > haven't checked.=C2=A0=20 > > > >=20 > > > > regvals[0] =3D val & 0xFF; > > > > regvals[1] =3D (val >> 8) & 0xFF;=C2=A0=20 > > >=20 > > > That is an endian conversion so use appropriate endian function to fi= ll it > > > efficiently and document clearly what is going on. > > >=20 > > >=20 > > > put_unaligned_le16() > > > =C2=A0=20 > > > >=20 > > > > return regmap_bulk_write(state->regmap,=C2=A0=20 > > > AD8460_HVDAC_DATA_WORD_LOW(index),=C2=A0=20 > > > > regvals,=C2=A0=20 > > > AD8460_DATA_BYTE_WORD_LENGTH); }=C2=A0=20 > > > >=20 > > > > =C2=A0 > > > > > > +}=C2=A0=20 > > > =C2=A0=20 > > > > > > + state->regmap =3D devm_regmap_init_spi(spi, > > > > > > &ad8460_regmap_config); > > > > > > + if (IS_ERR(state->regmap)) > > > > > > + return dev_err_probe(&spi->dev, PTR_ERR(state->regmap), > > > > > > + =C2=A0=C2=A0=C2=A0=C2=A0 "Failed to initialize regmap"); > > > > > > + > > > > > > + ret =3D devm_iio_dmaengine_buffer_setup_ext(&spi->dev, indio_= dev, > > > > > > +"tx", > > > > > > +=C2=A0=20 > > > > > IIO_BUFFER_DIRECTION_OUT); > > > > >=20 > > > > > Ah. I take back my binding comment. I assume this is mapping some > > > > > non standard interface for the parallel data flow?=C2=A0=20 > > > >=20 > > > > Yes, the HDL side doesn't follow yet the standard IIO backend from > > > > which this driver was tested=C2=A0=20 > > >=20 > > > Hmm. I'd like to see this brought inline with the other iio backend d= rivers if > > > possible.=C2=A0=20 > >=20 > > Does this mean that we would need to implement an AXI IP core on the > > FPGA side to be able to test this? >=20 > Don't think so.=C2=A0 That framework is meant to support any equivalent I= P. > So whatever you have should be supportable. Maybe it's somewhat of a stub > driver though if there isn't anything controllable. >=20 > It's Nuno's area of expertise though +CC. >=20 Hi Jonathan, Yeah, I did reply David (IIRC) about the very same question. In the design/= HW Mariel is working on the DAC is directly connected to the DMA core which is handle= d already by a proper dma controller driver. So in this case I'm really not seeing th= e backend need right now (maybe in the future we may have another design for this dev= ice that could justify for a backend device but no idea on that). As you mention, we could very well do a stub platform driver so we can use = the backend framework (like dma-backend or something) that could pretty much be= a stub for the DMA controller. But is it worth it though? We'd actually be "lying"= in terms of HW description as the DMA is a property of the actual converter. - Nuno S=C3=A1