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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id z14-20020a2eb52e000000b002b724063010sm2355545ljm.47.2023.10.25.01.41.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Oct 2023 01:41:12 -0700 (PDT) Message-ID: Date: Wed, 25 Oct 2023 10:41:10 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/10] clk: qcom: add the SM8650 Global Clock Controller driver Content-Language: en-US To: Neil Armstrong , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231025-topic-sm8650-upstream-clocks-v1-0-c89b59594caf@linaro.org> <20231025-topic-sm8650-upstream-clocks-v1-6-c89b59594caf@linaro.org> From: Konrad Dybcio In-Reply-To: <20231025-topic-sm8650-upstream-clocks-v1-6-c89b59594caf@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/25/23 09:32, Neil Armstrong wrote: > Add Global Clock Controller (GCC) support for SM8650 platform. > > Signed-off-by: Neil Armstrong > --- Just a couple remarks 1. looks like there's no usage of shared ops (corresponding to enable_safe_parent or something along these lines downstream) 2. none of the GDSCs have interesting flags.. I have this little cheat sheet that you may find handy: qcom,retain-regs -> RETAIN_FF_ENABLE qcom,support-hw-trigger + set_mode in driver -> HW_CONTROL qcom,no-status-check-on-disable -> VOTABLE qcom,reset-aon-logic -> AON_RESET domain-addr = clamp_io_ctrl 3. gcc_cpuss_ubwcp_clk_src uses the XO_A clock as parent, but it's not there in the ftbl.. Could you confirm whether this clock should even be accessed from HLOS? [...] > +static int gcc_sm8650_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + regmap = qcom_cc_map(pdev, &gcc_sm8650_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, > + ARRAY_SIZE(gcc_dfs_clocks)); > + if (ret) > + return ret; > + > + /* > + * Keep the critical clock always-On > + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, > + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, > + * gcc_video_xo_clk > + */ Could you make these comments inline, i.e. regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ ? Konrad