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Fri, 17 Oct 2025 05:35:45 -0700 (PDT) Message-ID: Subject: Re: [PATCH 3/6] spi: add multi_bus_mode field to struct spi_transfer From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Date: Fri, 17 Oct 2025 13:36:18 +0100 In-Reply-To: <66f94eb6-15a9-457f-a7b8-47710652a34b@baylibre.com> References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> <20251014-spi-add-multi-bus-support-v1-3-2098c12d6f5f@baylibre.com> <9269eadc1ea593e5bc8f5cad8061b48220f4d2b2.camel@gmail.com> <409ad505-8846-443e-8d71-baca3c9aef21@sirena.org.uk> <12db0930458ceb596010655736b0a67a0ad0ae53.camel@gmail.com> <8c7bf62a-c5dc-4e4d-8059-8abea15ba94e@sirena.org.uk> <9024f05854dcc3cc59345c0a3de900f57c4730d9.camel@gmail.com> <66f94eb6-15a9-457f-a7b8-47710652a34b@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-10-16 at 10:25 -0500, David Lechner wrote: > On 10/16/25 4:08 AM, Nuno S=C3=A1 wrote: > > On Wed, 2025-10-15 at 13:38 -0500, David Lechner wrote: > > > On 10/15/25 11:43 AM, Nuno S=C3=A1 wrote: > > > > On Wed, 2025-10-15 at 11:15 -0500, David Lechner wrote: > > > > > On 10/15/25 10:18 AM, Mark Brown wrote: > > > > > > On Wed, Oct 15, 2025 at 03:43:09PM +0100, Nuno S=C3=A1 wrote: > > > > > > > On Wed, 2025-10-15 at 13:01 +0100, Mark Brown wrote: > > > > > > > > On Wed, Oct 15, 2025 at 11:16:01AM +0100, Nuno S=C3=A1 wrot= e: > > > > > > > > > On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote: >=20 > ... >=20 > > >=20 > > > The AXI SPI Engine doesn't know how to do the quad SPI part yet thoug= h, so > > > it isn't something we could implement right now. > > >=20 > > > If we tried to do it with spi-buses =3D <8>; then we would end up wit= h the > > > "interleaved" bits (or nibbles depending on the wiring) that requires= the > > > extra IP block to sort out when using SPI offloading. Technically, we > > > could > >=20 > > I think that extra block already exists today. I was thinking the idea = was > > just: > >=20 > > // the case where we just have one channel with eg: 32 bits words (eg: = test > > patterns)=20 > > struct spi_transfer example =3D { > > rx_buf =3D rx_buf; > > len =3D 1; /* 1 32bit words */ >=20 > This would still need to be len =3D 4; since there are 4 bytes in a > 32-bit word. (If this was tx with SPI_MULTI_BUS_MODE_MIRROR, then > len =3D 1 would be correct, but for striping, it is still the length > of all data combined). Right, I was still thinking in the old stuff where the spi engine would alw= ays have len =3D 1 (which is nok) >=20 > > /* 4 lanes which is actually quadspi */ > > multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE;=20 > > }; >=20 > This will work with the caveat that for non-offload case, the software= =20 > will need to rearrange the bits in rx_buf into the correct order after > the spi_sync(). >=20 > For example, u8 *rx_buf will contain bits of the 32-bit word in the > following order: >=20 > rx_buf[0] =3D b28 b24 b20 b16 b12 b8 b4 b0 > rx_buf[1] =3D b29 b25 b21 b17 b13 b9 b5 b1 > rx_buf[2] =3D b30 b26 b22 b18 b14 b10 b6 b2 > rx_buf[3] =3D b31 b27 b23 b19 b15 b11 b7 b3 >=20 > The correct order of course would be (assuming little endian): >=20 >=20 > rx_buf[0] =3D b7 b6 b5 b4 b3 b2 b1 b0 I know, that's what the ad4030 driver has to do. - Nuno S=C3=A1