From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
To: Chris Morgan <macroalpha82@gmail.com>, dri-devel@lists.freedesktop.org
Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
sebastian.reichel@collabora.com, heiko@sntech.de,
conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org,
tzimmermann@suse.de, mripard@kernel.org,
maarten.lankhorst@linux.intel.com, simona@ffwll.ch,
airlied@gmail.com, quic_jesszhan@quicinc.com,
neil.armstrong@linaro.org, javierm@redhat.com, megi@xff.cz,
Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [PATCH 3/4] drm/panel: himax-hx8394: Add Support for Huiling hl055fhav028c
Date: Tue, 3 Jun 2025 18:00:53 -0700 [thread overview]
Message-ID: <cd47f14c-908c-4fa9-97eb-d2db4c90be1b@oss.qualcomm.com> (raw)
In-Reply-To: <20250603193930.323607-4-macroalpha82@gmail.com>
On 6/3/2025 12:39 PM, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the Huiling hl055fhav028c panel as used on the
> Gameforce Ace handheld gaming console. This panel uses a Himax HX8399C
> display controller and requires a sparsely documented vendor provided
> init sequence. The display resolution is 1080x1920 and is 70mm by 127mm
> as stated in the manufacturer's documentation.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
> drivers/gpu/drm/panel/panel-himax-hx8394.c | 142 +++++++++++++++++++++
> 1 file changed, 142 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c
> index ff994bf0e3cc..16e450b156b7 100644
> --- a/drivers/gpu/drm/panel/panel-himax-hx8394.c
> +++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c
> @@ -477,6 +477,147 @@ static const struct hx8394_panel_desc mchp_ac40t08a_desc = {
> .init_sequence = mchp_ac40t08a_init_sequence,
> };
>
> +/*
> + * HL055FHAV028C is based on Himax HX8399, so datasheet pages are
> + * slightly different than HX8394 based panels.
> + */
> +static void hl055fhav028c_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
> +{
> + /* 6.3.6 SETEXTC: Set extension command (B9h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,
> + 0xff, 0x83, 0x99);
> +
> + /* 6.3.17 SETOFFSET: Set offset voltage (D2h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETOFFSET,
> + 0x77);
> +
> + /* 6.3.1 SETPOWER: Set power (B1h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
> + 0x02, 0x04, 0x74, 0x94, 0x01, 0x32,
> + 0x33, 0x11, 0x11, 0xab, 0x4d, 0x56,
> + 0x73, 0x02, 0x02);
> +
> + /* 6.3.2 SETDISP: Set display related register (B2h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,
> + 0x00, 0x80, 0x80, 0xae, 0x05, 0x07,
> + 0x5a, 0x11, 0x00, 0x00, 0x10, 0x1e,
> + 0x70, 0x03, 0xd4);
> +
> + /* 6.3.3 SETCYC: Set display waveform cycles (B4h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,
> + 0x00, 0xff, 0x02, 0xc0, 0x02, 0xc0,
> + 0x00, 0x00, 0x08, 0x00, 0x04, 0x06,
> + 0x00, 0x32, 0x04, 0x0a, 0x08, 0x21,
> + 0x03, 0x01, 0x00, 0x0f, 0xb8, 0x8b,
> + 0x02, 0xc0, 0x02, 0xc0, 0x00, 0x00,
> + 0x08, 0x00, 0x04, 0x06, 0x00, 0x32,
> + 0x04, 0x0a, 0x08, 0x01, 0x00, 0x0f,
> + 0xb8, 0x01);
> +
> + /* 6.3.18 SETGIP0: Set GIP Option0 (D3h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x06, 0x00, 0x00, 0x10, 0x04, 0x00,
> + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
> + 0x00, 0x05, 0x05, 0x07, 0x00, 0x00,
> + 0x00, 0x05, 0x40);
> +
> + /* 6.3.19 Set GIP Option1 (D5h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,
> + 0x18, 0x18, 0x19, 0x19, 0x18, 0x18,
> + 0x21, 0x20, 0x01, 0x00, 0x07, 0x06,
> + 0x05, 0x04, 0x03, 0x02, 0x18, 0x18,
> + 0x18, 0x18, 0x18, 0x18, 0x2f, 0x2f,
> + 0x30, 0x30, 0x31, 0x31, 0x18, 0x18,
> + 0x18, 0x18);
> +
> + /* 6.3.20 Set GIP Option2 (D6h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,
> + 0x18, 0x18, 0x19, 0x19, 0x40, 0x40,
> + 0x20, 0x21, 0x02, 0x03, 0x04, 0x05,
> + 0x06, 0x07, 0x00, 0x01, 0x40, 0x40,
> + 0x40, 0x40, 0x40, 0x40, 0x2f, 0x2f,
> + 0x30, 0x30, 0x31, 0x31, 0x40, 0x40,
> + 0x40, 0x40);
> +
> + /* 6.3.21 Set GIP Option3 (D8h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,
> + 0xa2, 0xaa, 0x02, 0xa0, 0xa2, 0xa8,
> + 0x02, 0xa0, 0xb0, 0x00, 0x00, 0x00,
> + 0xb0, 0x00, 0x00, 0x00);
> +
> + /* 6.3.9 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
> + 0x01);
> +
> + /* 6.3.21 Set GIP Option3 (D8h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,
> + 0xb0, 0x00, 0x00, 0x00, 0xb0, 0x00,
> + 0x00, 0x00, 0xe2, 0xaa, 0x03, 0xf0,
> + 0xe2, 0xaa, 0x03, 0xf0);
> +
> + /* 6.3.9 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
> + 0x02);
> +
> + /* 6.3.21 Set GIP Option3 (D8h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,
> + 0xe2, 0xaa, 0x03, 0xf0, 0xe2, 0xaa,
> + 0x03, 0xf0);
> +
> + /* 6.3.9 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
> + 0x00);
> +
> + /* 6.3.4 SETVCOM: Set VCOM voltage (B6h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,
> + 0x7a, 0x7a);
> +
> + /* 6.3.26 SETGAMMA: Set gamma curve related setting (E0h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,
> + 0x00, 0x18, 0x27, 0x24, 0x5a, 0x68,
> + 0x79, 0x78, 0x81, 0x8a, 0x92, 0x99,
> + 0x9e, 0xa7, 0xaf, 0xb4, 0xb9, 0xc3,
> + 0xc7, 0xd1, 0xc6, 0xd4, 0xd5, 0x6c,
> + 0x67, 0x71, 0x77, 0x00, 0x00, 0x18,
> + 0x27, 0x24, 0x5a, 0x68, 0x79, 0x78,
> + 0x81, 0x8a, 0x92, 0x99, 0x9e, 0xa7,
> + 0xaf, 0xb4, 0xb9, 0xc3, 0xc7, 0xd1,
> + 0xc6, 0xd4, 0xd5, 0x6c, 0x67, 0x77);
> +
> + /* Unknown command, not listed in the HX8399-C datasheet (C6h) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2,
> + 0xff, 0xf9);
> +
> + /* 6.3.16 SETPANEL (CCh) */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,
> + 0x08);
> +}
> +
> +static const struct drm_display_mode hl055fhav028c_mode = {
> + .hdisplay = 1080,
> + .hsync_start = 1080 + 32,
> + .hsync_end = 1080 + 32 + 8,
> + .htotal = 1080 + 32 + 8 + 32,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 16,
> + .vsync_end = 1920 + 16 + 2,
> + .vtotal = 1920 + 16 + 2 + 14,
> + .clock = 134920,
> + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> + .width_mm = 70,
> + .height_mm = 127,
> +};
> +
> +static const struct hx8394_panel_desc hl055fhav028c_desc = {
> + .mode = &hl055fhav028c_mode,
> + .lanes = 4,
> + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
> + .format = MIPI_DSI_FMT_RGB888,
> + .init_sequence = hl055fhav028c_init_sequence,
> +};
> +
> static int hx8394_enable(struct drm_panel *panel)
> {
> struct hx8394 *ctx = panel_to_hx8394(panel);
> @@ -683,6 +824,7 @@ static void hx8394_remove(struct mipi_dsi_device *dsi)
>
> static const struct of_device_id hx8394_of_match[] = {
> { .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc },
> + { .compatible = "huiling,hl055fhav028c", .data = &hl055fhav028c_desc },
> { .compatible = "powkiddy,x55-panel", .data = &powkiddy_x55_desc },
> { .compatible = "microchip,ac40t08a-mipi-panel", .data = &mchp_ac40t08a_desc },
> { /* sentinel */ }
next prev parent reply other threads:[~2025-06-04 1:01 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-03 19:39 [PATCH 0/4] Add DSI Panel for Gameforce Ace Chris Morgan
2025-06-03 19:39 ` [PATCH 1/4] dt-bindings: vendor-prefixes: Add prefix for Huiling Chris Morgan
2025-06-04 11:29 ` Krzysztof Kozlowski
2025-06-03 19:39 ` [PATCH 2/4] dt-bindings: display: himax-hx8394: Add Huiling hl055fhav028c Chris Morgan
2025-06-04 11:30 ` Krzysztof Kozlowski
2025-06-04 11:35 ` Javier Martinez Canillas
2025-06-03 19:39 ` [PATCH 3/4] drm/panel: himax-hx8394: Add Support for " Chris Morgan
2025-06-04 1:00 ` Jessica Zhang [this message]
2025-06-04 11:36 ` Javier Martinez Canillas
2025-06-05 11:54 ` Diederik de Haas
2025-06-05 12:46 ` Heiko Stübner
2025-06-05 12:55 ` Diederik de Haas
2025-06-05 13:29 ` Chris Morgan
2025-06-03 19:39 ` [PATCH 4/4] arm64: dts: rockchip: Add DSI panel support for gameforce-ace Chris Morgan
2025-06-04 11:37 ` Javier Martinez Canillas
2025-06-05 6:55 ` (subset) [PATCH 0/4] Add DSI Panel for Gameforce Ace Neil Armstrong
2025-06-09 10:23 ` Heiko Stuebner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cd47f14c-908c-4fa9-97eb-d2db4c90be1b@oss.qualcomm.com \
--to=jessica.zhang@oss.qualcomm.com \
--cc=airlied@gmail.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=heiko@sntech.de \
--cc=javierm@redhat.com \
--cc=krzk+dt@kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=macroalpha82@gmail.com \
--cc=macromorgan@hotmail.com \
--cc=megi@xff.cz \
--cc=mripard@kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=quic_jesszhan@quicinc.com \
--cc=robh@kernel.org \
--cc=sebastian.reichel@collabora.com \
--cc=simona@ffwll.ch \
--cc=tzimmermann@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).