From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47E4324B29; Sun, 7 Jul 2024 14:00:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720360806; cv=none; b=lLKYTM+7OLt0vDwHiCTJuoUsrwDRAf2aEl1C8J8/YsZ1Pi6dm5IJK8dTE56SPs36FJXIxJGUcXLDPbS9JBRQzX/XUNagIYD3JeJCfju3ttODjIr70/yC0J9EjCN73oVEgxcHKsNAPhANkkL4lh9y6+R1JOwPhasKuzRgRwfMKMg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720360806; c=relaxed/simple; bh=w6E61bZ+Nc7fH6AkO+e1UuyFuM7XFN8xxnB02WH7ZKU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=nKqDZT1WksenriHTAA4T9kzhsfbr5eprCGD9xIDRvhZSjsOZkAJ1BbaGga7DIlSAhOLBbKF2OUqTFWaJTdRaf7TE29DIMsMdnWa1cVpuu9XHoVZtCLOTUoK+LVox60AQlq6O5ocY2c16+Bd5a9RMcLRiyPtRIJfXxILqnPJrfCI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WSLQIOrT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WSLQIOrT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D4B8C3277B; Sun, 7 Jul 2024 13:59:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720360805; bh=w6E61bZ+Nc7fH6AkO+e1UuyFuM7XFN8xxnB02WH7ZKU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=WSLQIOrT+HiXM06ezax1CgdZzJMHs2tG5p/jyZL40Lyw64OJOn7VqHCvKzOnIun9w s6ST+JTzdDi/wUlJxGDtpaa7S67wAm8LsvS3nk6EF2jmqHpACQtZmaZhEN9ITntz9h oSlOd+vaSa6FqkrEQqIC26H/duwTwWRglBg+m8+vqVtwj/uOUguCQ1apde1zAXaOKo r8adn0m09tsmfZgiuAspuVbUhn9e3m/WQFOH2bmo0g411k/tqr10rq7BEDXSGVGW6u xlHDmlI7kiCyi/i0l/1/L5E4GrkAOYIYX9gukSOar80Orpno/GMgL2BbmICI6SbMho eDEjO6rBIVHvg== Message-ID: Date: Sun, 7 Jul 2024 15:59:56 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine To: Liu Ying , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, tglx@linutronix.de References: <20240705090932.1880496-1-victor.liu@nxp.com> <20240705090932.1880496-3-victor.liu@nxp.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/07/2024 11:09, Liu Ying wrote: > i.MX8qxp Display Controller display engine consists of all processing units > that operate in a display clock domain. > > Signed-off-by: Liu Ying > --- > .../imx/fsl,imx8qxp-dc-display-engine.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml > new file mode 100644 > index 000000000000..dc9579897b76 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml > @@ -0,0 +1,166 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8qxp Display Controller Display Engine > + > +description: > + All Processing Units that operate in a display clock domain. Pixel pipeline > + is driven by a video timing and cannot be stalled. Implements all display > + specific processing. > + > +maintainers: > + - Liu Ying > + > +properties: > + compatible: > + const: fsl,imx8qxp-dc-display-engine > + > + reg: > + maxItems: 2 > + > + reg-names: > + items: > + - const: top > + - const: cfg > + > + resets: > + maxItems: 1 > + > + interrupts: > + maxItems: 3 > + > + interrupt-names: > + items: > + - const: shdload > + - const: framecomplete > + - const: seqcomplete > + > + power-domains: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > + ranges: true > + > + fsl,dc-de-id: > + description: Display Engine instance number > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1] No, drop. For the same reason as earlier patch. > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: video output Eh, mixing children with and without addresses is considered poor design. > + > +patternProperties: > + "^dither@[0-9a-f]+$": > + type: object > + additionalProperties: true > + > + properties: > + compatible: > + const: fsl,imx8qxp-dc-dither > + > + "^framegen@[0-9a-f]+$": > + type: object > + additionalProperties: true > + > + properties: > + compatible: > + const: fsl,imx8qxp-dc-framegen > + > + "^gammacor@[0-9a-f]+$": This looks like you are organizing bindings per your driver architecture. Best regards, Krzysztof