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[83.9.31.165]) by smtp.gmail.com with ESMTPSA id u22-20020ac24c36000000b004f857bdbb26sm1100686lfq.30.2023.06.22.04.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jun 2023 04:59:11 -0700 (PDT) Message-ID: Date: Thu, 22 Jun 2023 13:59:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 6/9] clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks Content-Language: en-US To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeffrey Hugo , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> <20230622-topic-8998clk-v1-6-5b7a0d6e98b1@linaro.org> From: Konrad Dybcio In-Reply-To: <20230622-topic-8998clk-v1-6-5b7a0d6e98b1@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22.06.2023 13:57, Konrad Dybcio wrote: > Some branch clocks are governed externally and we're only supposed to > send a request concerning their shutdown, not actually ensure it happens. > > Use the BRANCH_HALT_SKIP define to skip checking the halt bit. > > Signed-off-by: Konrad Dybcio > --- Whoops. Again, right after hitting send, I noticed this one was already sent with https://lore.kernel.org/linux-arm-msm/20230531-topic-8998_mmssclk-v1-0-2b5a8fc90991@linaro.org/ > drivers/clk/qcom/gcc-msm8998.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c > index cccb19cae481..ef410f52f09f 100644 > --- a/drivers/clk/qcom/gcc-msm8998.c > +++ b/drivers/clk/qcom/gcc-msm8998.c > @@ -2112,7 +2112,7 @@ static struct clk_branch gcc_gp3_clk = { > > static struct clk_branch gcc_bimc_gfx_clk = { > .halt_reg = 0x46040, > - .halt_check = BRANCH_HALT, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x46040, > .enable_mask = BIT(0), > @@ -2125,7 +2125,7 @@ static struct clk_branch gcc_bimc_gfx_clk = { > > static struct clk_branch gcc_gpu_bimc_gfx_clk = { > .halt_reg = 0x71010, > - .halt_check = BRANCH_HALT, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x71010, > .enable_mask = BIT(0), > @@ -2151,7 +2151,7 @@ static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { > > static struct clk_branch gcc_gpu_cfg_ahb_clk = { > .halt_reg = 0x71004, > - .halt_check = BRANCH_HALT, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x71004, > .enable_mask = BIT(0), >