[PATCH v2 00/10] SUNIV USB and PopStick support (and updating mailmap)

[PATCH v2 00/10] SUNIV USB and PopStick support (and updating mailmap)

[Icenowy Zheng]

This patchset introduces support for F1C100s' USB and SourceParts
PopStick board.

As I switched to a new mail address, and this patchset contains patches
authored before this change, a mailmap update is added.

The DT binding and driver support for SUNIV USB PHY/MUSB are added, in
addition to DT changes to the DTSI and Lichee Nano DT. A new DT is added
for SourceParts PopStick v1.1 board.

Icenowy Zheng (10):
  mailmap: update Icenowy Zheng's mail address
  dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
  dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
  phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
  musb: sunxi: add support for the F1C100s MUSB controller
  ARM: suniv: add USB-related device nodes
  ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
  dt-bindings: vendor-prefixes: add Source Parts
  dt-binding: arm: sunxi: add compatible strings for PopStick v1.1
  ARM: dts: suniv: add device tree for PopStick v1.1

 .mailmap                                      |   3 +
 .../devicetree/bindings/arm/sunxi.yaml        |   7 ++
 .../phy/allwinner,suniv-f1c100s-usb-phy.yaml  |  83 ++++++++++++++
 .../usb/allwinner,sun4i-a10-musb.yaml         |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/Makefile                    |   3 +-
 .../boot/dts/suniv-f1c100s-licheepi-nano.dts  |  16 +++
 arch/arm/boot/dts/suniv-f1c100s.dtsi          |  26 +++++
 .../boot/dts/suniv-f1c200s-popstick-v1.1.dts  | 101 ++++++++++++++++++
 drivers/phy/allwinner/phy-sun4i-usb.c         |  11 ++
 drivers/usb/musb/sunxi.c                      |   8 +-
 11 files changed, 258 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
 create mode 100644 arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts

-- 
2.37.1

[PATCH v2 01/10] mailmap: update Icenowy Zheng's mail address

[Icenowy Zheng]

Due to the SMTP provider adopted by AOSC applied some more restricted
rate limit that is not suitable for sending kernel patches, I switched
to a mailbox hosted on my own domain name now. In addition, there's a
single commit that is pushed to the mainline kernel tree during my
internship at Sipeed the last year.

Map two AOSC mail addresses (both aosc.io and aosc.xyz domain names) and
a defunct Sipeed mail address to the new mail address.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes since v1.

 .mailmap | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.mailmap b/.mailmap
index 380378e2db36..59b7130c3d1b 100644
--- a/.mailmap
+++ b/.mailmap
@@ -168,6 +168,9 @@ Henrik Rydberg <rydberg@bitmath.org>
 Herbert Xu <herbert@gondor.apana.org.au>
 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.io>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.xyz>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@sipeed.com>
 Jacob Shin <Jacob.Shin@amd.com>
 Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
 Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
-- 
2.37.1

Re: [PATCH v2 01/10] mailmap: update Icenowy Zheng's mail address

[Arnd Bergmann]

On Wed, Oct 12, 2022, at 7:55 AM, Icenowy Zheng wrote:
> Due to the SMTP provider adopted by AOSC applied some more restricted
> rate limit that is not suitable for sending kernel patches, I switched
> to a mailbox hosted on my own domain name now. In addition, there's a
> single commit that is pushed to the mainline kernel tree during my
> internship at Sipeed the last year.
>
> Map two AOSC mail addresses (both aosc.io and aosc.xyz domain names) and
> a defunct Sipeed mail address to the new mail address.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

I don't see a patch for updating the MAINTAINERS file here, if you
haven't already sent that another way, you should probably change
both at the same time.

As a driver maintainer, you can also apply for a kernel.org account
[https://korg.docs.kernel.org/accounts.html] and use that for
sending patches and forwarding to another address.

     Arnd

Re: [PATCH v2 01/10] mailmap: update Icenowy Zheng's mail address

[Icenowy Zheng]

在 2022-10-12星期三的 10:31 +0200，Arnd Bergmann写道：
> On Wed, Oct 12, 2022, at 7:55 AM, Icenowy Zheng wrote:
> > Due to the SMTP provider adopted by AOSC applied some more
> > restricted
> > rate limit that is not suitable for sending kernel patches, I
> > switched
> > to a mailbox hosted on my own domain name now. In addition, there's
> > a
> > single commit that is pushed to the mainline kernel tree during my
> > internship at Sipeed the last year.
> > 
> > Map two AOSC mail addresses (both aosc.io and aosc.xyz domain
> > names) and
> > a defunct Sipeed mail address to the new mail address.
> > 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> 
> I don't see a patch for updating the MAINTAINERS file here, if you
> haven't already sent that another way, you should probably change
> both at the same time.

Good point. If this patchset is going to have a v3, I will contain it
there; otherwise I will independently send it.

> 
> As a driver maintainer, you can also apply for a kernel.org account
> [https://korg.docs.kernel.org/accounts.html] and use that for
> sending patches and forwarding to another address.

Well I am in China now and not so easy to get my PGP key signed...

> 
>      Arnd

Re: [PATCH v2 01/10] mailmap: update Icenowy Zheng's mail address

[Arnd Bergmann]

On Wed, Oct 12, 2022, at 10:35 AM, Icenowy Zheng wrote:
> 在 2022-10-12星期三的 10:31 +0200，Arnd Bergmann写道：
>> On Wed, Oct 12, 2022, at 7:55 AM, Icenowy Zheng wrote:
>> 
>> I don't see a patch for updating the MAINTAINERS file here, if you
>> haven't already sent that another way, you should probably change
>> both at the same time.
>
> Good point. If this patchset is going to have a v3, I will contain it
> there; otherwise I will independently send it.

Ok. If you make a separate patch for the maintainers file, feel
free to send this to me at soc@kernel.org, I can then put it into
the fixes branch so it makes it into 6.1, otherwise I assume this
gets picked up through the normal path along with the rest of the
series.

>> As a driver maintainer, you can also apply for a kernel.org account
>> [https://korg.docs.kernel.org/accounts.html] and use that for
>> sending patches and forwarding to another address.
>
> Well I am in China now and not so easy to get my PGP key signed...

Right, that can be a problem. In an urgent case, you could probably
do a video meeting with someone you've previously met that is already
on the kernel keyring, but that is perhaps not worth the hassle
if your current setup otherwise works fine.

     Arnd

[PATCH v2 02/10] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY

[Icenowy Zheng]

Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
because it has only one OTG USB controller, no host-only OHCI/EHCI
controllers.

Add a binding document for it. Following the current situation of one
YAML file per SoC, this one is based on
allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits
removed. (The same driver in Linux, phy-sun4i-usb, covers all these
binding files now.)

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in v2:
- Clarify the relation with other phy-sun4i-usb bindings.
- Added Rob's ACK.

 .../phy/allwinner,suniv-f1c100s-usb-phy.yaml  | 83 +++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
new file mode 100644
index 000000000000..22ff8e0f2331
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner F1C100s USB PHY Device Tree Bindings
+
+maintainers:
+  - Chen-Yu Tsai <wens@csie.org>
+  - Maxime Ripard <mripard@kernel.org>
+
+properties:
+  "#phy-cells":
+    const: 1
+
+  compatible:
+    const: allwinner,suniv-f1c100s-usb-phy
+
+  reg:
+    maxItems: 1
+    description: PHY Control registers
+
+  reg-names:
+    const: phy_ctrl
+
+  clocks:
+    maxItems: 1
+    description: USB OTG PHY bus clock
+
+  clock-names:
+    const: usb0_phy
+
+  resets:
+    maxItems: 1
+    description: USB OTG reset
+
+  reset-names:
+    const: usb0_reset
+
+  usb0_id_det-gpios:
+    maxItems: 1
+    description: GPIO to the USB OTG ID pin
+
+  usb0_vbus_det-gpios:
+    maxItems: 1
+    description: GPIO to the USB OTG VBUS detect pin
+
+  usb0_vbus_power-supply:
+    description: Power supply to detect the USB OTG VBUS
+
+  usb0_vbus-supply:
+    description: Regulator controlling USB OTG VBUS
+
+required:
+  - "#phy-cells"
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+    #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
+    phy@1c13400 {
+        compatible = "allwinner,suniv-f1c100s-usb-phy";
+        reg = <0x01c13400 0x10>;
+        reg-names = "phy_ctrl";
+        clocks = <&ccu CLK_USB_PHY0>;
+        clock-names = "usb0_phy";
+        resets = <&ccu RST_USB_PHY0>;
+        reset-names = "usb0_reset";
+        #phy-cells = <1>;
+        usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
+    };
-- 
2.37.1

Re: [PATCH v2 02/10] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY

[Andre Przywara]

On Wed, 12 Oct 2022 13:55:54 +0800
Icenowy Zheng <uwu@icenowy.me> wrote:

> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
> 
> Add a binding document for it. Following the current situation of one
> YAML file per SoC, this one is based on
> allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits
> removed. (The same driver in Linux, phy-sun4i-usb, covers all these
> binding files now.)
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> Changes in v2:
> - Clarify the relation with other phy-sun4i-usb bindings.
> - Added Rob's ACK.
> 
>  .../phy/allwinner,suniv-f1c100s-usb-phy.yaml  | 83 +++++++++++++++++++
>  1 file changed, 83 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> new file mode 100644
> index 000000000000..22ff8e0f2331
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner F1C100s USB PHY Device Tree Bindings

I see that commit dd3cb467ebb56 [1] discourages the redundant "Device Tree
Bindings" suffix in the title name, so I think you should remove that.

The rest looks alright to me, compared against the manual and what the
driver expects, so with that fixed:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dd3cb467ebb56

> +
> +maintainers:
> +  - Chen-Yu Tsai <wens@csie.org>
> +  - Maxime Ripard <mripard@kernel.org>
> +
> +properties:
> +  "#phy-cells":
> +    const: 1
> +
> +  compatible:
> +    const: allwinner,suniv-f1c100s-usb-phy
> +
> +  reg:
> +    maxItems: 1
> +    description: PHY Control registers
> +
> +  reg-names:
> +    const: phy_ctrl
> +
> +  clocks:
> +    maxItems: 1
> +    description: USB OTG PHY bus clock
> +
> +  clock-names:
> +    const: usb0_phy
> +
> +  resets:
> +    maxItems: 1
> +    description: USB OTG reset
> +
> +  reset-names:
> +    const: usb0_reset
> +
> +  usb0_id_det-gpios:
> +    maxItems: 1
> +    description: GPIO to the USB OTG ID pin
> +
> +  usb0_vbus_det-gpios:
> +    maxItems: 1
> +    description: GPIO to the USB OTG VBUS detect pin
> +
> +  usb0_vbus_power-supply:
> +    description: Power supply to detect the USB OTG VBUS
> +
> +  usb0_vbus-supply:
> +    description: Regulator controlling USB OTG VBUS
> +
> +required:
> +  - "#phy-cells"
> +  - compatible
> +  - clocks
> +  - clock-names
> +  - reg
> +  - reg-names
> +  - resets
> +  - reset-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +    #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
> +    #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
> +
> +    phy@1c13400 {
> +        compatible = "allwinner,suniv-f1c100s-usb-phy";
> +        reg = <0x01c13400 0x10>;
> +        reg-names = "phy_ctrl";
> +        clocks = <&ccu CLK_USB_PHY0>;
> +        clock-names = "usb0_phy";
> +        resets = <&ccu RST_USB_PHY0>;
> +        reset-names = "usb0_reset";
> +        #phy-cells = <1>;
> +        usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> +    };

[PATCH v2 03/10] dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string

[Icenowy Zheng]

Allwinner F1C100s has a hybrid MUSB controller between the A10 one and
the A33 one.

Add a compatible string for it.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes since v1.

 .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
index 8992eff6ce38..9ae634280bf4 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -17,6 +17,7 @@ properties:
       - const: allwinner,sun6i-a31-musb
       - const: allwinner,sun8i-a33-musb
       - const: allwinner,sun8i-h3-musb
+      - const: allwinner,suniv-f1c100s-musb
       - items:
           - enum:
               - allwinner,sun8i-a83t-musb
-- 
2.37.1

Re: [PATCH v2 03/10] dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string

[Krzysztof Kozlowski]

On 12/10/2022 01:55, Icenowy Zheng wrote:
> Allwinner F1C100s has a hybrid MUSB controller between the A10 one and
> the A33 one.
> 
> Add a compatible string for it.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 04/10] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC

[Icenowy Zheng]

The F1C100s SoC has one USB OTG port connected to a MUSB controller.

Add support for its USB PHY.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes since v1.

 drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 3a3831f6059a..2f94cb77637b 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
 	sun8i_v3s_phy,
 	sun50i_a64_phy,
 	sun50i_h6_phy,
+	suniv_f1c100s_phy,
 };
 
 struct sun4i_usb_phy_cfg {
@@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+	.num_phys = 1,
+	.type = suniv_f1c100s_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.num_phys = 3,
 	.type = sun4i_a10_phy,
@@ -988,6 +997,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
 	  .data = &sun50i_a64_cfg},
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
+	  .data = &suniv_f1c100s_cfg },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
-- 
2.37.1

Re: [PATCH v2 04/10] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC

[Jernej Škrabec]

Hi Icenowy,

Dne sreda, 12. oktober 2022 ob 07:55:56 CEST je Icenowy Zheng napisal(a):
> The F1C100s SoC has one USB OTG port connected to a MUSB controller.
> 
> Add support for its USB PHY.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> No changes since v1.
> 
>  drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> b/drivers/phy/allwinner/phy-sun4i-usb.c index 3a3831f6059a..2f94cb77637b
> 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
>  	sun8i_v3s_phy,
>  	sun50i_a64_phy,
>  	sun50i_h6_phy,
> +	suniv_f1c100s_phy,
>  };
> 
>  struct sun4i_usb_phy_cfg {
> @@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device
> *pdev) return 0;
>  }
> 
> +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
> +	.num_phys = 1,
> +	.type = suniv_f1c100s_phy,

I think you should just use sun4i_a10_phy. It has no special handling. I don't 
see a point adding new phy types if there is no special cases for it.

Best regards,
Jernej

> +	.disc_thresh = 3,
> +	.phyctl_offset = REG_PHYCTL_A10,
> +	.dedicated_clocks = true,
> +};
> +
>  static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
>  	.num_phys = 3,
>  	.type = sun4i_a10_phy,
> @@ -988,6 +997,8 @@ static const struct of_device_id
> sun4i_usb_phy_of_match[] = { { .compatible =
> "allwinner,sun50i-a64-usb-phy",
>  	  .data = &sun50i_a64_cfg},
>  	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = 
&sun50i_h6_cfg },
> +	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
> +	  .data = &suniv_f1c100s_cfg },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> --
> 2.37.1

Re: [PATCH v2 04/10] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC

[Icenowy Zheng]

在 2022-10-12星期三的 23:21 +0200，Jernej Škrabec写道：
> Hi Icenowy,
> 
> Dne sreda, 12. oktober 2022 ob 07:55:56 CEST je Icenowy Zheng
> napisal(a):
> > The F1C100s SoC has one USB OTG port connected to a MUSB
> > controller.
> > 
> > Add support for its USB PHY.
> > 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > No changes since v1.
> > 
> >  drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > b/drivers/phy/allwinner/phy-sun4i-usb.c index
> > 3a3831f6059a..2f94cb77637b
> > 100644
> > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > @@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
> >         sun8i_v3s_phy,
> >         sun50i_a64_phy,
> >         sun50i_h6_phy,
> > +       suniv_f1c100s_phy,
> >  };
> > 
> >  struct sun4i_usb_phy_cfg {
> > @@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct
> > platform_device
> > *pdev) return 0;
> >  }
> > 
> > +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
> > +       .num_phys = 1,
> > +       .type = suniv_f1c100s_phy,
> 
> I think you should just use sun4i_a10_phy. It has no special
> handling. I don't 
> see a point adding new phy types if there is no special cases for it.

Sounds reasonable, although I think we should finally drop .type and
use only describing items.

> 
> Best regards,
> Jernej
> 
> > +       .disc_thresh = 3,
> > +       .phyctl_offset = REG_PHYCTL_A10,
> > +       .dedicated_clocks = true,
> > +};
> > +
> >  static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> >         .num_phys = 3,
> >         .type = sun4i_a10_phy,
> > @@ -988,6 +997,8 @@ static const struct of_device_id
> > sun4i_usb_phy_of_match[] = { { .compatible =
> > "allwinner,sun50i-a64-usb-phy",
> >           .data = &sun50i_a64_cfg},
> >         { .compatible = "allwinner,sun50i-h6-usb-phy", .data = 
> &sun50i_h6_cfg },
> > +       { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> > +         .data = &suniv_f1c100s_cfg },
> >         { },
> >  };
> >  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> > --
> > 2.37.1
> 
> 
> 

Re: Re: [PATCH v2 04/10] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC

[Jernej Škrabec]

Dne četrtek, 13. oktober 2022 ob 10:49:51 CEST je Icenowy Zheng napisal(a):
> 在 2022-10-12星期三的 23:21 +0200，Jernej Škrabec写道：
> 
> > Hi Icenowy,
> > 
> > Dne sreda, 12. oktober 2022 ob 07:55:56 CEST je Icenowy Zheng
> > 
> > napisal(a):
> > > The F1C100s SoC has one USB OTG port connected to a MUSB
> > > controller.
> > > 
> > > Add support for its USB PHY.
> > > 
> > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > > ---
> > > No changes since v1.
> > > 
> > >  drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
> > >  1 file changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > b/drivers/phy/allwinner/phy-sun4i-usb.c index
> > > 3a3831f6059a..2f94cb77637b
> > > 100644
> > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > @@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
> > >         sun8i_v3s_phy,
> > >         sun50i_a64_phy,
> > >         sun50i_h6_phy,
> > > +       suniv_f1c100s_phy,
> > >  };
> > > 
> > >  struct sun4i_usb_phy_cfg {
> > > @@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct
> > > platform_device
> > > *pdev) return 0;
> > >  }
> > > 
> > > +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
> > > +       .num_phys = 1,
> > > +       .type = suniv_f1c100s_phy,
> > 
> > I think you should just use sun4i_a10_phy. It has no special
> > handling. I don't
> > see a point adding new phy types if there is no special cases for it.
> 
> Sounds reasonable, although I think we should finally drop .type and
> use only describing items.

That would be even better. Will you do it?

> 
> > Best regards,
> > Jernej
> > 
> > > +       .disc_thresh = 3,
> > > +       .phyctl_offset = REG_PHYCTL_A10,
> > > +       .dedicated_clocks = true,
> > > +};
> > > +
> > >  static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> > >         .num_phys = 3,
> > >         .type = sun4i_a10_phy,
> > > @@ -988,6 +997,8 @@ static const struct of_device_id
> > > sun4i_usb_phy_of_match[] = { { .compatible =
> > > "allwinner,sun50i-a64-usb-phy",
> > >           .data = &sun50i_a64_cfg},
> > >         { .compatible = "allwinner,sun50i-h6-usb-phy", .data =
> > 
> > &sun50i_h6_cfg },
> > 
> > > +       { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> > > +         .data = &suniv_f1c100s_cfg },
> > >         { },
> > >  };
> > >  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> > > --
> > > 2.37.1

Re: Re: [PATCH v2 04/10] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC

[Icenowy Zheng]

在 2022-10-13星期四的 20:25 +0200，Jernej Škrabec写道：
> Dne četrtek, 13. oktober 2022 ob 10:49:51 CEST je Icenowy Zheng
> napisal(a):
> > 在 2022-10-12星期三的 23:21 +0200，Jernej Škrabec写道：
> > 
> > > Hi Icenowy,
> > > 
> > > Dne sreda, 12. oktober 2022 ob 07:55:56 CEST je Icenowy Zheng
> > > 
> > > napisal(a):
> > > > The F1C100s SoC has one USB OTG port connected to a MUSB
> > > > controller.
> > > > 
> > > > Add support for its USB PHY.
> > > > 
> > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > > > ---
> > > > No changes since v1.
> > > > 
> > > >  drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
> > > >  1 file changed, 11 insertions(+)
> > > > 
> > > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > b/drivers/phy/allwinner/phy-sun4i-usb.c index
> > > > 3a3831f6059a..2f94cb77637b
> > > > 100644
> > > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > @@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
> > > >         sun8i_v3s_phy,
> > > >         sun50i_a64_phy,
> > > >         sun50i_h6_phy,
> > > > +       suniv_f1c100s_phy,
> > > >  };
> > > > 
> > > >  struct sun4i_usb_phy_cfg {
> > > > @@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct
> > > > platform_device
> > > > *pdev) return 0;
> > > >  }
> > > > 
> > > > +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
> > > > +       .num_phys = 1,
> > > > +       .type = suniv_f1c100s_phy,
> > > 
> > > I think you should just use sun4i_a10_phy. It has no special
> > > handling. I don't
> > > see a point adding new phy types if there is no special cases for
> > > it.
> > 
> > Sounds reasonable, although I think we should finally drop .type
> > and
> > use only describing items.
> 
> That would be even better. Will you do it?

At least not now.

But I will at least drop suniv_f1c100s_phy in the next revision.

> 
> > 
> > > Best regards,
> > > Jernej
> > > 
> > > > +       .disc_thresh = 3,
> > > > +       .phyctl_offset = REG_PHYCTL_A10,
> > > > +       .dedicated_clocks = true,
> > > > +};
> > > > +
> > > >  static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> > > >         .num_phys = 3,
> > > >         .type = sun4i_a10_phy,
> > > > @@ -988,6 +997,8 @@ static const struct of_device_id
> > > > sun4i_usb_phy_of_match[] = { { .compatible =
> > > > "allwinner,sun50i-a64-usb-phy",
> > > >           .data = &sun50i_a64_cfg},
> > > >         { .compatible = "allwinner,sun50i-h6-usb-phy", .data =
> > > 
> > > &sun50i_h6_cfg },
> > > 
> > > > +       { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> > > > +         .data = &suniv_f1c100s_cfg },
> > > >         { },
> > > >  };
> > > >  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> > > > --
> > > > 2.37.1
> 
> 

[PATCH v2 05/10] musb: sunxi: add support for the F1C100s MUSB controller

[Icenowy Zheng]

The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
region to be claimed.

Add support for it.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes since v1.

 drivers/usb/musb/sunxi.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 7f9a999cd5ff..4b368d16a73a 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -722,14 +722,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
 	INIT_WORK(&glue->work, sunxi_musb_work);
 	glue->host_nb.notifier_call = sunxi_musb_host_notifier;
 
-	if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+	if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+	    of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
 		set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
+	}
 
 	if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
 		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
 
 	if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
-	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+	    of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
 		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
 		set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
 	}
@@ -815,6 +818,7 @@ static const struct of_device_id sunxi_musb_match[] = {
 	{ .compatible = "allwinner,sun6i-a31-musb", },
 	{ .compatible = "allwinner,sun8i-a33-musb", },
 	{ .compatible = "allwinner,sun8i-h3-musb", },
+	{ .compatible = "allwinner,suniv-f1c100s-musb", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, sunxi_musb_match);
-- 
2.37.1

Re: [PATCH v2 05/10] musb: sunxi: add support for the F1C100s MUSB controller

[Jernej Škrabec]

Hi Icenowy,

Dne sreda, 12. oktober 2022 ob 07:55:57 CEST je Icenowy Zheng napisal(a):
> The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
> region to be claimed.
> 
> Add support for it.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> No changes since v1.
> 
>  drivers/usb/musb/sunxi.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
> index 7f9a999cd5ff..4b368d16a73a 100644
> --- a/drivers/usb/musb/sunxi.c
> +++ b/drivers/usb/musb/sunxi.c
> @@ -722,14 +722,17 @@ static int sunxi_musb_probe(struct platform_device
> *pdev) INIT_WORK(&glue->work, sunxi_musb_work);
>  	glue->host_nb.notifier_call = sunxi_musb_host_notifier;
> 
> -	if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
> +	if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
> +	    of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
>  		set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
> +	}
> 
>  	if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
>  		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
> 
>  	if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
> -	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
> +	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
> +	    of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {

All that should be eventually converted to quirks. But for now:
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

>  		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
>  		set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
>  	}
> @@ -815,6 +818,7 @@ static const struct of_device_id sunxi_musb_match[] = {
>  	{ .compatible = "allwinner,sun6i-a31-musb", },
>  	{ .compatible = "allwinner,sun8i-a33-musb", },
>  	{ .compatible = "allwinner,sun8i-h3-musb", },
> +	{ .compatible = "allwinner,suniv-f1c100s-musb", },
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, sunxi_musb_match);
> --
> 2.37.1

[PATCH v2 06/10] ARM: suniv: add USB-related device nodes

[Icenowy Zheng]

The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.

Add their device tree node.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes since v1.

 arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0edc1724407b..a01541ba42c5 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@ mmc1: mmc@1c10000 {
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb@1c13000 {
+			compatible = "allwinner,suniv-f1c100s-musb";
+			reg = <0x01c13000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <26>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			allwinner,sram = <&otg_sram 1>;
+			status = "disabled";
+		};
+
+		usbphy: phy@1c13400 {
+			compatible = "allwinner,suniv-f1c100s-usb-phy";
+			reg = <0x01c13400 0x10>;
+			reg-names = "phy_ctrl";
+			clocks = <&ccu CLK_USB_PHY0>;
+			clock-names = "usb0_phy";
+			resets = <&ccu RST_USB_PHY0>;
+			reset-names = "usb0_reset";
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,suniv-f1c100s-ccu";
 			reg = <0x01c20000 0x400>;
-- 
2.37.1

Re: [PATCH v2 06/10] ARM: suniv: add USB-related device nodes

[Andre Przywara]

On Wed, 12 Oct 2022 13:55:58 +0800
Icenowy Zheng <uwu@icenowy.me> wrote:

Hi,

> The suniv SoC has a USB OTG controller and a USB PHY like other
> Allwinner SoCs.
> 
> Add their device tree node.

Looks alright to me, checked against the manual, also compared against
some other Allwinner USB DT nodes. Also passes the binding and DTB checks.

Just one small question below, but nevertheless:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> No changes since v1.
> 
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 0edc1724407b..a01541ba42c5 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -133,6 +133,32 @@ mmc1: mmc@1c10000 {
>  			#size-cells = <0>;
>  		};
>  
> +		usb_otg: usb@1c13000 {
> +			compatible = "allwinner,suniv-f1c100s-musb";
> +			reg = <0x01c13000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <26>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			allwinner,sram = <&otg_sram 1>;

What is this "1" for? I see it all over the other Allwinner SRAM
properties, but can't find any documentation about that number, nor can I
see that it would be used in the code.

Does anyone know?

Cheers,
Andre

> +			status = "disabled";
> +		};
> +
> +		usbphy: phy@1c13400 {
> +			compatible = "allwinner,suniv-f1c100s-usb-phy";
> +			reg = <0x01c13400 0x10>;
> +			reg-names = "phy_ctrl";
> +			clocks = <&ccu CLK_USB_PHY0>;
> +			clock-names = "usb0_phy";
> +			resets = <&ccu RST_USB_PHY0>;
> +			reset-names = "usb0_reset";
> +			#phy-cells = <1>;
> +			status = "disabled";
> +		};
> +
>  		ccu: clock@1c20000 {
>  			compatible = "allwinner,suniv-f1c100s-ccu";
>  			reg = <0x01c20000 0x400>;

Re: [PATCH v2 06/10] ARM: suniv: add USB-related device nodes

[Icenowy Zheng]

在 2022-10-24星期一的 15:16 +0100，Andre Przywara写道：
> On Wed, 12 Oct 2022 13:55:58 +0800
> Icenowy Zheng <uwu@icenowy.me> wrote:
> 
> Hi,
> 
> > The suniv SoC has a USB OTG controller and a USB PHY like other
> > Allwinner SoCs.
> > 
> > Add their device tree node.
> 
> Looks alright to me, checked against the manual, also compared
> against
> some other Allwinner USB DT nodes. Also passes the binding and DTB
> checks.
> 
> Just one small question below, but nevertheless:
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > No changes since v1.
> > 
> >  arch/arm/boot/dts/suniv-f1c100s.dtsi | 26
> > ++++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > index 0edc1724407b..a01541ba42c5 100644
> > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > @@ -133,6 +133,32 @@ mmc1: mmc@1c10000 {
> >                         #size-cells = <0>;
> >                 };
> >  
> > +               usb_otg: usb@1c13000 {
> > +                       compatible = "allwinner,suniv-f1c100s-
> > musb";
> > +                       reg = <0x01c13000 0x0400>;
> > +                       clocks = <&ccu CLK_BUS_OTG>;
> > +                       resets = <&ccu RST_BUS_OTG>;
> > +                       interrupts = <26>;
> > +                       interrupt-names = "mc";
> > +                       phys = <&usbphy 0>;
> > +                       phy-names = "usb";
> > +                       extcon = <&usbphy 0>;
> > +                       allwinner,sram = <&otg_sram 1>;
> 
> What is this "1" for? I see it all over the other Allwinner SRAM
> properties, but can't find any documentation about that number, nor
> can I
> see that it would be used in the code.

It means mapping the SRAM to dedicated device instead of CPU.

This information is available in previous sunxi-sram.txt binding, but
lost when converting to json schema, maybe because it does not fit well
in json schema.

> 
> Does anyone know?
> 
> Cheers,
> Andre
> 
> > +                       status = "disabled";
> > +               };
> > +
> > +               usbphy: phy@1c13400 {
> > +                       compatible = "allwinner,suniv-f1c100s-usb-
> > phy";
> > +                       reg = <0x01c13400 0x10>;
> > +                       reg-names = "phy_ctrl";
> > +                       clocks = <&ccu CLK_USB_PHY0>;
> > +                       clock-names = "usb0_phy";
> > +                       resets = <&ccu RST_USB_PHY0>;
> > +                       reset-names = "usb0_reset";
> > +                       #phy-cells = <1>;
> > +                       status = "disabled";
> > +               };
> > +
> >                 ccu: clock@1c20000 {
> >                         compatible = "allwinner,suniv-f1c100s-ccu";
> >                         reg = <0x01c20000 0x400>;
> 

[PATCH v2 07/10] ARM: suniv: f1c100s: enable USB on Lichee Pi Nano

[Icenowy Zheng]

Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected
to the USB pins of the SoC and ID pin connected to PE2 GPIO.

Enable the USB functionality.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes since v1.

 .../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381cb..1935d8c8855b 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 #include "suniv-f1c100s.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	model = "Lichee Pi Nano";
 	compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@ flash@0 {
 	};
 };
 
+&otg_sram {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pe_pins>;
 	status = "okay";
 };
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+	status = "okay";
+};
-- 
2.37.1

Re: [PATCH v2 07/10] ARM: suniv: f1c100s: enable USB on Lichee Pi Nano

[Krzysztof Kozlowski]

On 12/10/2022 01:55, Icenowy Zheng wrote:
> Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected
> to the USB pins of the SoC and ID pin connected to PE2 GPIO.
> 
> Enable the USB functionality.

Use subject prefixes matching the subsystem (git log --oneline -- ...).

This is a DTS change.

> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> No changes since v1.
> 
>  .../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 

Best regards,
Krzysztof

[PATCH v2 08/10] dt-bindings: vendor-prefixes: add Source Parts

[Icenowy Zheng]

Source Parts Inc. [1] is a company that makes a series of SBCs, SoMs,
etc under a brand called Popcorn Computer [2].

Add it to the vendor prefixes list.

[1] https://source.parts/
[2] https://popcorncomputer.com/

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
New patch introduced in v2.

 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6e323a380294..035ef859fbc5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1203,6 +1203,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sourceparts,.*":
+    description: Source Parts Inc.
   "^spansion,.*":
     description: Spansion Inc.
   "^sparkfun,.*":
-- 
2.37.1

Re: [PATCH v2 08/10] dt-bindings: vendor-prefixes: add Source Parts

[Krzysztof Kozlowski]

On 12/10/2022 01:56, Icenowy Zheng wrote:
> Source Parts Inc. [1] is a company that makes a series of SBCs, SoMs,
> etc under a brand called Popcorn Computer [2].
> 
> Add it to the vendor prefixes list.


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 09/10] dt-binding: arm: sunxi: add compatible strings for PopStick v1.1

[Icenowy Zheng]

SourceParts PopStick is a F1C200s-based stick-shaped SBC.

Add a compatible string list for its v1.1 version (the first public
one).

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
New patch introduced in v2.

 Documentation/devicetree/bindings/arm/sunxi.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 3ad1cd50e3fe..c6e0ad7f461d 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -807,6 +807,13 @@ properties:
           - const: sinlinx,sina33
           - const: allwinner,sun8i-a33
 
+      - description: SourceParts PopStick v1.1
+        items:
+          - const: sourceparts,popstick-v1.1
+          - const: sourceparts,popstick
+          - const: allwinner,suniv-f1c200s
+          - const: allwinner,suniv-f1c100s
+
       - description: SL631 Action Camera with IMX179
         items:
           - const: allwinner,sl631-imx179
-- 
2.37.1

Re: [PATCH v2 09/10] dt-binding: arm: sunxi: add compatible strings for PopStick v1.1

[Krzysztof Kozlowski]

On 12/10/2022 01:56, Icenowy Zheng wrote:
> SourceParts PopStick is a F1C200s-based stick-shaped SBC.
> 
> Add a compatible string list for its v1.1 version (the first public
> one).
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> New patch introduced in v2.
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 09/10] dt-binding: arm: sunxi: add compatible strings for PopStick v1.1

[Andre Przywara]

On Wed, 12 Oct 2022 13:56:01 +0800
Icenowy Zheng <uwu@icenowy.me> wrote:

Hi Icenowy,

> SourceParts PopStick is a F1C200s-based stick-shaped SBC.
> 
> Add a compatible string list for its v1.1 version (the first public
> one).

If v1.0 (or anything prior) never made it to the outside world, I don't
think we need to mention that in the public bindings.
In general Linux seems to discourage support for unreleased hardware, so I
think you can just drop the "sourceparts,popstick-v1.1" name.

Cheers,
Andre

> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> New patch introduced in v2.
> 
>  Documentation/devicetree/bindings/arm/sunxi.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 3ad1cd50e3fe..c6e0ad7f461d 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -807,6 +807,13 @@ properties:
>            - const: sinlinx,sina33
>            - const: allwinner,sun8i-a33
>  
> +      - description: SourceParts PopStick v1.1
> +        items:
> +          - const: sourceparts,popstick-v1.1
> +          - const: sourceparts,popstick
> +          - const: allwinner,suniv-f1c200s
> +          - const: allwinner,suniv-f1c100s
> +
>        - description: SL631 Action Camera with IMX179
>          items:
>            - const: allwinner,sl631-imx179

Re: [PATCH v2 09/10] dt-binding: arm: sunxi: add compatible strings for PopStick v1.1

[Icenowy Zheng]

在 2022-10-24星期一的 15:17 +0100，Andre Przywara写道：
> On Wed, 12 Oct 2022 13:56:01 +0800
> Icenowy Zheng <uwu@icenowy.me> wrote:
> 
> Hi Icenowy,
> 
> > SourceParts PopStick is a F1C200s-based stick-shaped SBC.
> > 
> > Add a compatible string list for its v1.1 version (the first public
> > one).
> 
> If v1.0 (or anything prior) never made it to the outside world, I
> don't
> think we need to mention that in the public bindings.
> In general Linux seems to discourage support for unreleased hardware,
> so I
> think you can just drop the "sourceparts,popstick-v1.1" name.

There's going to be v2.0, which is quite different to v1.1.

> 
> Cheers,
> Andre
> 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > New patch introduced in v2.
> > 
> >  Documentation/devicetree/bindings/arm/sunxi.yaml | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
> > b/Documentation/devicetree/bindings/arm/sunxi.yaml
> > index 3ad1cd50e3fe..c6e0ad7f461d 100644
> > --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> > +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> > @@ -807,6 +807,13 @@ properties:
> >            - const: sinlinx,sina33
> >            - const: allwinner,sun8i-a33
> >  
> > +      - description: SourceParts PopStick v1.1
> > +        items:
> > +          - const: sourceparts,popstick-v1.1
> > +          - const: sourceparts,popstick
> > +          - const: allwinner,suniv-f1c200s
> > +          - const: allwinner,suniv-f1c100s
> > +
> >        - description: SL631 Action Camera with IMX179
> >          items:
> >            - const: allwinner,sl631-imx179
> 

[PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1

[Icenowy Zheng]

PopStick is a minimal Allwinner F1C200s dongle, with its USB controller
wired to a USB Type-A port, a SD slot and a SPI NAND flash on board, and
an on-board CH340 USB-UART converted connected to F1C200s's UART0.

Add a device tree for it. As F1C200s is just F1C100s with a different
DRAM chip co-packaged, directly use F1C100s DTSI here.

This commit covers the v1.1 version of this board, which is now shipped.
v1.0 is some internal sample that have not been shipped at all.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
New patch introduced in v2.

 arch/arm/boot/dts/Makefile                    |   3 +-
 .../boot/dts/suniv-f1c200s-popstick-v1.1.dts  | 101 ++++++++++++++++++
 2 files changed, 103 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6aa7dc4db2fc..0249c07bd8a6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1391,7 +1391,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
 dtb-$(CONFIG_MACH_SUNIV) += \
-	suniv-f1c100s-licheepi-nano.dtb
+	suniv-f1c100s-licheepi-nano.dtb \
+	suniv-f1c200s-popstick-v1.1.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
 	tegra20-acer-a500-picasso.dtb \
 	tegra20-asus-tf101.dtb \
diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
new file mode 100644
index 000000000000..121dfc6f609d
--- /dev/null
+++ b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Popcorn Computer PopStick v1.1";
+	compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
+		     "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
+
+	aliases {
+		mmc0 = &mmc0;
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&mmc0 {
+	cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
+	bus-width = <4>;
+	disable-wp;
+	status = "okay";
+	vmmc-supply = <&reg_vcc3v3>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot-with-spl";
+				reg = <0x0 0x100000>;
+			};
+
+			ubi@100000 {
+				label = "ubi";
+				reg = <0x100000 0x7f00000>;
+			};
+		};
+	};
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pe_pins>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
-- 
2.37.1

Re: [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1

[Clément Péron]

Hi Icenowy,

On Wed, 12 Oct 2022 at 07:57, Icenowy Zheng <uwu@icenowy.me> wrote:
>
> PopStick is a minimal Allwinner F1C200s dongle, with its USB controller
> wired to a USB Type-A port, a SD slot and a SPI NAND flash on board, and
> an on-board CH340 USB-UART converted connected to F1C200s's UART0.
>
> Add a device tree for it. As F1C200s is just F1C100s with a different
> DRAM chip co-packaged, directly use F1C100s DTSI here.
>
> This commit covers the v1.1 version of this board, which is now shipped.
> v1.0 is some internal sample that have not been shipped at all.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> New patch introduced in v2.
>
>  arch/arm/boot/dts/Makefile                    |   3 +-
>  .../boot/dts/suniv-f1c200s-popstick-v1.1.dts  | 101 ++++++++++++++++++
>  2 files changed, 103 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6aa7dc4db2fc..0249c07bd8a6 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1391,7 +1391,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
>         sun9i-a80-optimus.dtb \
>         sun9i-a80-cubieboard4.dtb
>  dtb-$(CONFIG_MACH_SUNIV) += \
> -       suniv-f1c100s-licheepi-nano.dtb
> +       suniv-f1c100s-licheepi-nano.dtb \
> +       suniv-f1c200s-popstick-v1.1.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>         tegra20-acer-a500-picasso.dtb \
>         tegra20-asus-tf101.dtb \
> diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
> new file mode 100644
> index 000000000000..121dfc6f609d
> --- /dev/null
> +++ b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
> + */
> +
> +/dts-v1/;
> +#include "suniv-f1c100s.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +       model = "Popcorn Computer PopStick v1.1";
> +       compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
> +                    "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
> +
> +       aliases {
> +               mmc0 = &mmc0;
> +               serial0 = &uart0;
> +               spi0 = &spi0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led {
> +                       function = LED_FUNCTION_STATUS;
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
> +                       linux,default-trigger = "heartbeat";
> +               };
> +       };
> +
> +       reg_vcc3v3: vcc3v3 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vcc3v3";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +       };
> +};
> +
> +&mmc0 {
> +       cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
> +       bus-width = <4>;
> +       disable-wp;
> +       status = "okay";
> +       vmmc-supply = <&reg_vcc3v3>;
> +};
> +
> +&spi0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&spi0_pc_pins>;
> +       status = "okay";
> +
> +       flash@0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "spi-nand";
> +               reg = <0>;
> +               spi-max-frequency = <40000000>;
> +
> +               partitions {
> +                       compatible = "fixed-partitions";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       partition@0 {
> +                               label = "u-boot-with-spl";
> +                               reg = <0x0 0x100000>;
> +                       };
> +
> +                       ubi@100000 {
> +                               label = "ubi";
> +                               reg = <0x100000 0x7f00000>;
> +                       };
> +               };
> +       };
> +};
> +
> +&otg_sram {

Nitpick, but this should be alphabetically ordered no?

> +       status = "okay";
> +};
> +
> +&uart0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&uart0_pe_pins>;
> +       status = "okay";
> +};
> +
> +&usb_otg {
> +       dr_mode = "peripheral";
> +       status = "okay";
> +};
> +
> +&usbphy {
> +       status = "okay";
> +};
> --
> 2.37.1
>
>

Re: [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1

[Krzysztof Kozlowski]

On 12/10/2022 01:56, Icenowy Zheng wrote:
> PopStick is a minimal Allwinner F1C200s dongle, with its USB controller
> wired to a USB Type-A port, a SD slot and a SPI NAND flash on board, and
> an on-board CH340 USB-UART converted connected to F1C200s's UART0.


(...)

> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led {
> +			function = LED_FUNCTION_STATUS;
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	reg_vcc3v3: vcc3v3 {

Generic node names, so at least generic "regulator" prefix or suffix.

> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +};
> +
> +&mmc0 {
> +	cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
> +	bus-width = <4>;
> +	disable-wp;
> +	status = "okay";

Keep status as last property.

> +	vmmc-supply = <&reg_vcc3v3>;
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi0_pc_pins>;
> +	status = "okay";
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "spi-nand";
> +		reg = <0>;

compatible and reg are by convention the first properties.

> +		spi-max-frequency = <40000000>;
> +

Best regards,
Krzysztof

Re: [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1

[Andre Przywara]

On Wed, 12 Oct 2022 13:56:02 +0800
Icenowy Zheng <uwu@icenowy.me> wrote:

Hi,

> PopStick is a minimal Allwinner F1C200s dongle, with its USB controller
> wired to a USB Type-A port, a SD slot and a SPI NAND flash on board, and
> an on-board CH340 USB-UART converted connected to F1C200s's UART0.
> 
> Add a device tree for it. As F1C200s is just F1C100s with a different
> DRAM chip co-packaged, directly use F1C100s DTSI here.
> 
> This commit covers the v1.1 version of this board, which is now shipped.
> v1.0 is some internal sample that have not been shipped at all.

As mentioned in the other patch, if that is the case, I don't think we
need to bother about the version number in the filename and compatible
strings, especially if a v1.0 will never be upstreamed. If there are users
of the internal version still, they can use an explicit "v1.0" in their
downstream versions.

So apart from what Krzysztof and Clement already mentioned, the DT itself
looks fine to me otherwise. I also ran dt-validate on it, and used it as a
base for another F1C200s board.

Cheers,
Andre

> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> New patch introduced in v2.
> 
>  arch/arm/boot/dts/Makefile                    |   3 +-
>  .../boot/dts/suniv-f1c200s-popstick-v1.1.dts  | 101 ++++++++++++++++++
>  2 files changed, 103 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6aa7dc4db2fc..0249c07bd8a6 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1391,7 +1391,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
>  	sun9i-a80-optimus.dtb \
>  	sun9i-a80-cubieboard4.dtb
>  dtb-$(CONFIG_MACH_SUNIV) += \
> -	suniv-f1c100s-licheepi-nano.dtb
> +	suniv-f1c100s-licheepi-nano.dtb \
> +	suniv-f1c200s-popstick-v1.1.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>  	tegra20-acer-a500-picasso.dtb \
>  	tegra20-asus-tf101.dtb \
> diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
> new file mode 100644
> index 000000000000..121dfc6f609d
> --- /dev/null
> +++ b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
> + */
> +
> +/dts-v1/;
> +#include "suniv-f1c100s.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	model = "Popcorn Computer PopStick v1.1";
> +	compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
> +		     "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
> +
> +	aliases {
> +		mmc0 = &mmc0;
> +		serial0 = &uart0;
> +		spi0 = &spi0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led {
> +			function = LED_FUNCTION_STATUS;
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	reg_vcc3v3: vcc3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +};
> +
> +&mmc0 {
> +	cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
> +	bus-width = <4>;
> +	disable-wp;
> +	status = "okay";
> +	vmmc-supply = <&reg_vcc3v3>;
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi0_pc_pins>;
> +	status = "okay";
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "spi-nand";
> +		reg = <0>;
> +		spi-max-frequency = <40000000>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "u-boot-with-spl";
> +				reg = <0x0 0x100000>;
> +			};
> +
> +			ubi@100000 {
> +				label = "ubi";
> +				reg = <0x100000 0x7f00000>;
> +			};
> +		};
> +	};
> +};
> +
> +&otg_sram {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pe_pins>;
> +	status = "okay";
> +};
> +
> +&usb_otg {
> +	dr_mode = "peripheral";
> +	status = "okay";
> +};
> +
> +&usbphy {
> +	status = "okay";
> +};