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([2a01:e0a:3d9:2080:25ab:4e12:265b:4b6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45dcff67787sm237340005e9.16.2025.09.09.05.27.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Sep 2025 05:27:33 -0700 (PDT) Message-ID: Date: Tue, 9 Sep 2025 14:27:31 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v3 3/5] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex To: Dmitry Baryshkov Cc: Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org References: <20250908-topic-x1e80100-hdmi-v3-0-c53b0f2bc2fb@linaro.org> <20250908-topic-x1e80100-hdmi-v3-3-c53b0f2bc2fb@linaro.org> <7dzfcuvr45h4iailtjutqjev7lofoqu7w6ob77gehgmy7mctpk@k7oob4wj3c7a> <14d58c6d-ca20-4349-8031-9906a4539fef@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 09/09/2025 13:16, Dmitry Baryshkov wrote: > On Tue, Sep 09, 2025 at 09:14:49AM +0200, Neil Armstrong wrote: >> On 08/09/2025 23:14, Dmitry Baryshkov wrote: >>> On Mon, Sep 08, 2025 at 03:04:20PM +0200, Neil Armstrong wrote: >>>> The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top >>>> of a combo glue to route either lanes to the 4 shared physical lanes. >>>> >>>> The routing of the lanes can be: >>>> - 2 DP + 2 USB3 >>>> - 4 DP >>>> - 2 USB3 >>>> >>>> The layout of the lanes was designed to be mapped and swapped >>>> related to the USB-C Power Delivery negociation, so it supports >>>> a finite set of mappings inherited by the USB-C Altmode layouts. >>>> >>>> Nevertheless those QMP Comby PHY can be used to drive a DisplayPort >>>> connector, DP->HDMI bridge, USB3 A Connector, etc... without >>>> an USB-C connector and no PD events. >>>> >>>> Document the data-lanes on numbered port@0 out endpoints, >>>> allowing us to document the lanes mapping to DisplayPort >>>> and/or USB3 connectors/peripherals. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>>> .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 59 +++++++++++++++++++++- >>>> 1 file changed, 58 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml >>>> index 5005514d7c3a1e4a8893883497fd204bc04e12be..51e0d0983091af0b8a5170ac34a05ab0acc435a3 100644 >>>> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml >>>> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml >>>> @@ -81,10 +81,67 @@ properties: >>>> ports: >>>> $ref: /schemas/graph.yaml#/properties/ports >>>> + >>>> properties: >>>> port@0: >>>> - $ref: /schemas/graph.yaml#/properties/port >>>> + $ref: /schemas/graph.yaml#/$defs/port-base >>>> description: Output endpoint of the PHY >>>> + unevaluatedProperties: false >>>> + >>>> + properties: >>>> + endpoint: >>>> + $ref: /schemas/graph.yaml#/$defs/endpoint-base >>>> + unevaluatedProperties: false >>>> + >>>> + endpoint@0: >>>> + $ref: /schemas/graph.yaml#/$defs/endpoint-base >>>> + description: Display Port Output lanes of the PHY when used with static mapping >>>> + unevaluatedProperties: false >>>> + >>>> + properties: >>>> + data-lanes: >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>>> + minItems: 2 >>> >>> Nit: DP can work in a 1-lane mode. Do we nned to support that in the PHY? >> >> So the PHY already supports 1-lane, but the QMP Combo only supports >> mapping 2+2 or 4, but nevetheless we can still decscribe 1 lane in DT >> int both in & out endpoint and still should work fine. >> >> Do you think this should be done now ? > > Do we support it in the PHY hardware? The PHY definitely supports 1 lanes, in fact DP the code will cycle over 4, 2 and 1 lane. Neil > >> >> Neil >> >>> >>>> + maxItems: 4 >>>> + oneOf: >>>> + - items: # DisplayPort 2 lanes, normal orientation >>>> + - const: 0 >>>> + - const: 1 >>>> + - items: # DisplayPort 2 lanes, flipped orientation >>>> + - const: 3 >>>> + - const: 2 >>>> + - items: # DisplayPort 4 lanes, normal orientation >>>> + - const: 0 >>>> + - const: 1 >>>> + - const: 2 >>>> + - const: 3 >>>> + - items: # DisplayPort 4 lanes, flipped orientation >>>> + - const: 3 >>>> + - const: 2 >>>> + - const: 1 >>>> + - const: 0 >>>> + required: >>>> + - data-lanes >>>> + >>>> + endpoint@1: >>>> + $ref: /schemas/graph.yaml#/$defs/endpoint-base >>>> + description: USB Output lanes of the PHY when used with static mapping >>>> + unevaluatedProperties: false >>>> + >>>> + properties: >>>> + data-lanes: >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>>> + minItems: 2 >>>> + oneOf: >>>> + - items: # USB3, normal orientation >>>> + - const: 1 >>>> + - const: 0 >>>> + - items: # USB3, flipped orientation >>>> + - const: 2 >>>> + - const: 3 >>>> + >>>> + required: >>>> + - data-lanes >>>> port@1: >>>> $ref: /schemas/graph.yaml#/properties/port >>>> >>>> -- >>>> 2.34.1 >>>> >>> >> >