Re: [PATCH v2 2/2] fpga manager: Add Xilinx slave serial SPI driver

[Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>]

On 21.2.2017 16:17, Anatolij Gustschin wrote:
> On Tue, 21 Feb 2017 15:51:18 +0100
> Michal Simek michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org wrote:
> ...
>>>> What's the hw configuration?  
>>>
>>> I used Spartan-6 for testing. But the driver might work with other
>>> Xilinx FPGAs, so I didn't add exact hw description.  
>>
>> ok. I expect this is spartan-6 next to another SoC and you use spi for
>> that another SoC and you connect.
> 
> yes, it is MVEBU SoC, I'm using orion_spi driver. The connection is
> unidirectional SPI.

ok. That means only dout (din fpga) and clk out (fpga clk in) and gpio
handling for others signals.

> 
>> I think it will be good to extend that example and add also spi device
>> node to see where this should be placed.
> 
> You mean the example in the binding description? I can add there
> something like:

yes in binding doc.

> 
> Usage example for full FPGA configuration:
> 
> fpga-region0 {
> 	compatible = "fpga-region";
> 	fpga-mgr = <&fpga_mgr_spi>;
> 	#address-cells = <0x1>;
> 	#size-cells = <0x1>;
> };
> 
> &spi1 {
> 	status = "okay";
> 
> 	fpga_mgr_spi: fpga-mgr@0 {
> 		compatible = "xlnx,fpga-slave-serial";
> 		reg = <0>;
> 		spi-max-frequency = <60000000>;
> 		spi-cpha;
> 		done-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
> 		prog_b-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
> 	};
> }; 

Right I would even replace &spi1 with full node to see content but this
is also good.

Thanks,
Michal


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