From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69CA7F9C8 for ; Mon, 6 Nov 2023 07:53:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ofG0kCc5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E34C7C433C9; Mon, 6 Nov 2023 07:53:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699257236; bh=1lvQWl4CfXhED/r0/C0UpDtEwhQ6AYy9bJQipe3ejXU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ofG0kCc5SbUIgrx/dTCQm9AwEADHP45pCfaAeoAHH8SrbN+CBJTvbWqPm4ngtiuHI 7LunnXGceG5/cVHyyBElA3a9+DvIBu2VAnpBLCeUHDI4q60GtoaXcl+qkNlq4dpxi+ xsnjr/+xs9e67yR5AFhyaoXKOdQkbJQDs+CMzlmNzjFauP2dKjfi1UdAkwOkzDFoRg vdp5qz6hX8ceGdOilo8IS1krv0YiChtOdIUeJAVLoG98vxmWMqIAMXN5Tvl6ywyzOo HDWC9R3B0RevLw7TGbT0hPuqz8HDE8+f+lw4o/+N7fVsoq72EVqzmMEfcRfZesJuFD F+3kE6/iTAUfg== Message-ID: Date: Mon, 6 Nov 2023 08:53:44 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] PCI: mediatek-gen3: Add power and reset control feature for downstream component Content-Language: en-US To: Jian Yang , AngeloGioacchino Del Regno , Bjorn Helgaas , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Matthias Brugger , Rob Herring , Jianjun Wang Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Chuanjia.Liu@mediatek.com, Jieyy.Yang@mediatek.com, Qizhong.Cheng@mediatek.com, Jianguo.Zhang@mediatek.com, Bartosz Golaszewski , Abel Vesa References: <20231106061220.21485-1-jian.yang@mediatek.com> <20231106061220.21485-3-jian.yang@mediatek.com> From: Krzysztof Kozlowski Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 06/11/2023 07:12, Jian Yang wrote: > From: "jian.yang" > > Make MediaTek's controller driver capable of controlling power > supplies and reset pin of a downstream component in power-on and > power-off process. > > Some downstream components (e.g., a WIFI chip) may need an extra > reset other than PERST# and their power supplies, depending on > the requirements of platform, may need to controlled by their > parent's driver. To meet the requirements described above, I add this > feature to MediaTek's PCIe controller driver as an optional feature. NAK, strong NAK. This should be done in a generic way because nothing here is specific to Mediatek. You just implement power sequencing of devices through quirks specific to one controller. Work with others to provide common solution. https://lpc.events/event/17/contributions/1507/ Best regards, Krzysztof