From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7167AC433F5 for ; Thu, 3 Mar 2022 10:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230059AbiCCKS0 (ORCPT ); Thu, 3 Mar 2022 05:18:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232214AbiCCKSY (ORCPT ); Thu, 3 Mar 2022 05:18:24 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A60EB3D for ; Thu, 3 Mar 2022 02:17:37 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id r65so2834502wma.2 for ; Thu, 03 Mar 2022 02:17:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=TtOHWLLsa7rSXRza0fGN1cBKMNwfwygfgSB4i7ej/Go=; b=Nbxsqfpf4U//4kMEYQgwampDN3L5Q2TZvU6x4HLIh5rHGeSfTWOiwOWf7WlZqw6Frz zabhNvVrT6tq8E8cRpfzQby2OfWLCvBQS6NEKRHlj/5MZ486/unuIlHEcozP6A2obxrZ vgvn9NR7WrxE6k4h/FVtUhMxA0XamBacTNXmPndxgT1s1Gzq1iOClFR7LzN8VEfyDUNC CPyh7ZV2CDvjdanG5kRemUYkgHYqpusnawgCP2gFBEL0axzKiQyl7FN0TM/0pSmF7XrP rg+gzo7zHRPIMjtAOSzVsLtTBGl1VLlODl7eu5qVrzYcg95eWFhHCKqTy7XYy/L5UnL1 6HXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=TtOHWLLsa7rSXRza0fGN1cBKMNwfwygfgSB4i7ej/Go=; b=LLiqMA4X6jkwOjSlOAvHiHdOo7QsiEbZIOZDwUpzl3UUVUmvOHHac1QY2sO8LAJiQn IiCfi1TAJtR/yLS/OI431rmASfuT5HOEZttx0fVGJjoHlvEmUevHxCSWqHXe7F3HZwMF JxLaP6FQ7IPVWj4PBuBSJ0ZaaUJflKMNEwii5yUl8TykfWeXHbU7iqCPpUbzdh2bzEj7 HU4BM52YfPTJGp2V+Yk7qb4Dx+N6KqYbIFctFLBXKvvBEIvQtlaX42Yp5BWjvNkyh7eh T293mnXMl0jo1GMj7CBRdAhm58V+qcCkubM5jnU/YV/GFckXTolP3k52YJ14e4LSk9k5 /LyQ== X-Gm-Message-State: AOAM532ClRLki5Fowtk7MqH6EDWzXBHz9KdVbPUEjlJrLnVD759ZgKdz xrNmFvk0oeHQtved/BcPdlnG6Q== X-Google-Smtp-Source: ABdhPJymkgSussHvNIxK2wwqP7NcLV6g47ibW+vjezWNLiFeFT+TfibQHdlBZqfWNbFWWCD8pOD30Q== X-Received: by 2002:a05:600c:4401:b0:387:1bcb:af41 with SMTP id u1-20020a05600c440100b003871bcbaf41mr2793032wmn.101.1646302655488; Thu, 03 Mar 2022 02:17:35 -0800 (PST) Received: from ?IPV6:2a01:e34:ed2f:f020:b9e3:8853:bc0:bb98? ([2a01:e34:ed2f:f020:b9e3:8853:bc0:bb98]) by smtp.googlemail.com with ESMTPSA id e18-20020adfdbd2000000b001e4bbbe5b92sm1713098wrj.76.2022.03.03.02.17.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Mar 2022 02:17:34 -0800 (PST) Message-ID: Date: Thu, 3 Mar 2022 11:17:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v8 2/2] clocksource: Add Intel Keem Bay timer support Content-Language: en-US To: "Sanil, Shruthi" , "tglx@linutronix.de" , "robh+dt@kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Cc: "andriy.shevchenko@linux.intel.com" , "mgross@linux.intel.com" , "Thokala, Srikanth" , "Raja Subramanian, Lakshmi Bai" , "Sangannavar, Mallikarjunappa" References: <20220222095654.9097-1-shruthi.sanil@intel.com> <20220222095654.9097-3-shruthi.sanil@intel.com> <91653d8d-1dc6-0170-2c3c-1187b0bad899@linaro.org> <23f86de0-3869-ee22-812d-ba610bac48b3@linaro.org> <3ff11b85-249f-2f47-cbc4-41d2ab6d168f@linaro.org> From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 03/03/2022 07:18, Sanil, Shruthi wrote: [ ... ] >>>>>>> + if (!(val & TIM_CONFIG_PRESCALER_ENABLE)) { + >>>>>>> pr_err("%pOF: Prescaler is not enabled\n", np); + ret = >>>>>>> -ENODEV; + } >>>>>> >>>>>> Why bail out instead of enabling the prescalar ? >>>>> >>>>> Because it is a secure register and it would be updated by >>>>> the bootloader. >>>> Should it be considered as a firmware bug ? >>> >>> No. This is a common driver across products in the series and >>> enablement of this bit depends on the project requirements. Hence >>> to be sure from driver, we added this check to avoid >>> initialization of the driver in the case where it cannot be >>> functional. >> >> I'm not sure to get the meaning of 'project requirements' but (for >> my understanding) why not describe the timer in the DT for such >> projects? >> > > OK, I understand your point now. We can control the driver > initialization from device tree binding rather than add a check in > the driver. But isn't it good to have a check, if enabling of the bit > is missed out in the FW? This can help in debugging. So if the description is in the DT but the prescaler bit is not enabled then the firmware is buggy, IIUC. Yeah, this check would help, may be add more context in the error message, eg. "Firmware has not enabled the prescaler bit" or something like that Thanks for the clarification -- D. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog