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([2a01:5a8:51e:a2d5:41ab:52ed:e3e9:4896]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879528dcc7sm1076503966b.29.2026.01.19.02.43.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jan 2026 02:43:52 -0800 (PST) Message-ID: Date: Mon, 19 Jan 2026 12:43:50 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] dt-bindings: clock: add exynos8890 SoC To: Krzysztof Kozlowski Cc: Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251017161334.1295955-1-ivo.ivanov.ivanov1@gmail.com> <20251017161334.1295955-2-ivo.ivanov.ivanov1@gmail.com> <20251022-affable-arrogant-coucal-3f7fbc@kuoka> Content-Language: en-US From: Ivaylo Ivanov Ivanov In-Reply-To: <20251022-affable-arrogant-coucal-3f7fbc@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 22.10.25 10:44, Krzysztof Kozlowski wrote: > On Fri, Oct 17, 2025 at 07:13:29PM +0300, Ivaylo Ivanov wrote: >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: samsung,exynos8890-cmu-aud >> + >> + then: >> + properties: >> + clocks: >> + items: >> + - description: External reference clock (76.8 MHz) >> + - description: CMU_AUD PLL clock (from CMU_TOP) >> + >> + clock-names: >> + items: >> + - const: oscclk >> + - const: pll >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: samsung,exynos8890-cmu-bus0 >> + >> + then: >> + properties: >> + clocks: >> + items: >> + - description: External reference clock (76.8 MHz) >> + - description: CMU_BUS0 ACLK 528MHz clock (from CMU_TOP) >> + - description: CMU_BUS0 ACLK 200MHz clock (from CMU_TOP) >> + - description: CMU_BUS0 PCLK 132MHz clock (from CMU_TOP) >> + >> + clock-names: >> + items: >> + - const: oscclk >> + - const: "528" >> + - const: "200" >> + - const: "132" > > We do not want the frequency here, for sure not frequency alone. There > is no such code/syntax. Really. Please do not invent your own style. > That's just pclk. You describe here the logical name of this clock > input. > > ACLK is AXI bus clock, so if this block receives only one ACLK, then > this is just "axi" or "bus". Recently we were calling this "bus". > > Same in other places. If two AXI bus clocks come in, they could be named > bus0 and bus1, or in this case - because these are sources for > generating further ACLKs - bus_528 and bus_200, to indicate that one > will be for AXI bus clocked 528 MHz and other for 200 MHz. > > Please wait for some other opinions, because same rule I would like to > apply to ExynosAuto, Artpec and Google GS. > > @Raghav Sharma, @Alim Akhtar, @Sam Protsenko, @Peter Griffin, @André > Draszik - share your thoughs please? > > And to clarify in simple terms for others or for the future: > 1. HCLK would be the AHB bus, so also bus. Both ACLK and HCLK are for > memory accesses. > 2. PCLK is APB bus, for registers. > 3. SCLK is for main operation of the block (called special clock, but no > clue what is so special about it). > So the consensus is to do something like this.. - const: oscclk - const: bus_528 - const: bus_200 - const: pclk .., right? Mentioned people haven't replied. I'm asking because I think it'd be more straightforward to go with just aclk_528 pclk_132 sclk_... or axi_528 apb_132. What do you think? Best regards, Ivaylo >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: samsung,exynos8890-cmu-bus1 >> + ... > Best regards, > Krzysztof >