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([2a01:e0a:106d:1080:d6d6:c397:9229:b35c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4888a72baa8sm495589675e9.15.2026.04.08.05.35.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 05:35:22 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 14:35:22 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support To: Konrad Dybcio , jsandom@axon.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com> <20260407-rb5gen2-dts-v2-5-d0c7f447ee73@axon.com> <4359bb07-d848-4b77-b1a9-f1c6f53caa10@oss.qualcomm.com> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <4359bb07-d848-4b77-b1a9-f1c6f53caa10@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/8/26 11:57, Konrad Dybcio wrote: > On 4/7/26 5:46 PM, Joe Sandom via B4 Relay wrote: >> From: Joe Sandom >> >> The RB5gen2 is an embedded development platform for the >> QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550). > > [...] > > >> + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */ >> + /* Workaround is to use bit-banged I2C */ > > Interesting.. I was under the impression that it was only an issue on > RB1 and RB2 boards.. perhaps we're missing some magic register write.. On the SM8650-HDK, the HDMI i2c is shared with the battmgr in ADSP, causing a lot of issues... the only solution is [1] to declare the bus shared and use GPI DMA. I assume it's the same here. Sharing the same bus between APPS and ADSP is a weird feat... It seems that having 26 i2c busses and 212 gpios available on the system is not enough. [1] https://lore.kernel.org/all/20241129144357.2008465-1-quic_msavaliy@quicinc.com/ > > > [...] > >> + pinctrl-names = "default"; >> + pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>, >> + <&pmk8550_sleep_clk>; > > nit: let's keep the order of > > property-n > property-names > > file-wide > > [...] > >> +&sdhc_2 { >> + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; >> + >> + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; >> + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; >> + pinctrl-names = "default", "sleep"; >> + >> + vmmc-supply = <&vreg_l9b_2p9>; >> + vqmmc-supply = <&vreg_l8b_1p8>; >> + >> + max-sd-hs-hz = <37000000>; > > Are you sure you want to overwrite that? The value in the SoC DTSI is > set to half a MHz higher > > >> + >> + no-sdio; >> + no-mmc; >> + >> + status = "okay"; >> +}; >> + >> +&sleep_clk { >> + clock-frequency = <32764>; >> +}; >> + >> +&spi11 { >> + status = "okay"; >> + >> + can@0 { >> + compatible = "microchip,mcp2518fd"; >> + reg = <0>; >> + interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>; >> + clocks = <&clk40m>; >> + spi-max-frequency = <10000000>; >> + vdd-supply = <&vreg_l14b_3p2>; >> + xceiver-supply = <&vreg_l14b_3p2>; > > It may be that for this chip to actually be able to communiate with devices > on the bus, you need to set the new 'microchip,xstbyen' property > > see: > > https://lore.kernel.org/linux-arm-msm/20260321135031.3107408-1-viken.dadhaniya@oss.qualcomm.com/ > > [...] > >> +&tlmm { >> + gpio-reserved-ranges = <32 8>; > > Would you happen to know what these pins are connected to, and if > so, add a comment (like in arch/arm64/boot/dts/qcom/x1-crd.dtsi)? > > > >> + >> + bt_default: bt-default-state { >> + pins = "gpio81"; > > It would be best to keep these entries ordered by pin idx > >> + function = "gpio"; >> + drive-strength = <16>; >> + bias-disable; >> + }; >> + >> + sw_ctrl_default: sw-ctrl-default-state { >> + pins = "gpio82"; >> + function = "gpio"; >> + bias-pull-down; >> + }; >> + >> + lt9611_irq_pin: lt9611-irq-state { >> + pins = "gpio40"; >> + function = "gpio"; >> + bias-disable; >> + }; >> + >> + lt9611_rst_pin: lt9611-rst-state { >> + pins = "gpio7"; >> + function = "gpio"; >> + output-high; > > You shouldn't need to assert the GPIO state in the pin entry node > - the driver should take care of that > > >> + }; >> + >> + ntn0_en: ntn0-en-state { >> + pins = "gpio67"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + ntn1_en: ntn1-en-state { >> + pins = "gpio42"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + upd_1p05_en: upd-1p05-en-state { >> + pins = "gpio179"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; > > I don't know if pulling up an active-high pin is what you want > (there's some more occurences) > > Konrad