From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B4B0C77B7F for ; Tue, 16 May 2023 11:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232952AbjEPLND (ORCPT ); Tue, 16 May 2023 07:13:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232887AbjEPLMp (ORCPT ); Tue, 16 May 2023 07:12:45 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37E6A7284 for ; Tue, 16 May 2023 04:11:24 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3f42c86543bso56699605e9.3 for ; Tue, 16 May 2023 04:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20221208.gappssmtp.com; s=20221208; t=1684235439; x=1686827439; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=ioKORldIiYtB2SsGKnyxrBw0xwGmK5RidmBBlL5Ztds=; b=40g2ESP3KvxEEYuVtdIXFyMVaWbC1e7CZd1xVEqbSAkTCEUtoem9DC0tYoJW4uRXQQ 48Qixe8+UYVFllhjeqX3m45D+820Ig2NvrNRGs8DfDLYZ9vA0+x6IXrTjuaHU0kWXZ9A bABF4AKGh1gBzJXTQ+FNckD3xPvPwQ1bLpwxOO1db1fVd4JD+X/dezTBXDH5FjB2CfKv bnXBsmhqLKIU3MTz1z/sPbI/ycX0KrIn7uB4K5GitA6vUtVrqju8pKahtdpWmOFZnCxM n2339rx66eyunXwUWDFq1Q00DEJjnwPDFSHWTFs6CZBLHP44V80PV+YU1gUpBdvnpcmU OaEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684235439; x=1686827439; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ioKORldIiYtB2SsGKnyxrBw0xwGmK5RidmBBlL5Ztds=; b=Fd180h7Qvy6jaSws1tR8hraTeTV3OrYK6M1ZA0diIydPAdVtR/6UFKKCogApngcgaV hMSpFVH0jvqhCLO3MuKJ6NcdtC/3ncTojRKQEh4yM4lkds/byHrOmq9Ejj57px/N3u0h tZqfVbkSnetf0n6e5Lj7PRbD5ABvnKNzUS6R6VkuoPiZdUpwn/5bTkOqyt/0aFwRhscP v3To8u7kHbWw8EIiR5CO68Shq/K9G8OSUuVQ7awxXECg/PgVlt3ec/9WZblk0qYHZWe/ gZ3Y79JJUhZEFPsSubL0voZYrAN2PqmKpIVvTSOOYLUeoNr+M6E6x4ZNy1Vj4Ir1FTOI xYsQ== X-Gm-Message-State: AC+VfDy1o7TC5bmvK4oOCF60Ejt6H+K0H4UpyrCA8ifpJGyC7mz5m+H3 i7o6j8rZG/ljjDa5YeJxmYhxIA== X-Google-Smtp-Source: ACHHUZ5R6+MuvE6h14q57HcZGLB0AA9F4N+zYdvtEsrXQsbxZuCoO7tuvAUaio+gGs0oh0bRHN7INA== X-Received: by 2002:adf:f344:0:b0:308:d687:c1f9 with SMTP id e4-20020adff344000000b00308d687c1f9mr10930163wrp.63.1684235439550; Tue, 16 May 2023 04:10:39 -0700 (PDT) Received: from [192.168.0.105] (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id c5-20020a5d63c5000000b003090cb7a9e6sm2262351wrw.31.2023.05.16.04.10.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 May 2023 04:10:38 -0700 (PDT) Message-ID: Date: Tue, 16 May 2023 13:10:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 23/23] arm64: zynqmp: Add phase tags marking Content-Language: en-US To: Michal Simek , linux-kernel@vger.kernel.org, michal.simek@xilinx.com, git@xilinx.com Cc: Amit Kumar Mahapatra , Harini Katakam , Krzysztof Kozlowski , Laurent Pinchart , Michael Grzeschik , Michael Tretter , Parth Gajjar , Piyush Mehta , Radhey Shyam Pandey , Rob Herring , Robert Hancock , Sai Krishna Potthuri , Srinivas Neeli , Tanmay Shah , Vishal Sagar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com> From: Michal Simek In-Reply-To: <48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 5/2/23 15:35, Michal Simek wrote: > bootph-all as phase tag was added to dt-schema > (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. > That's why add it also to Linux to be aligned with bootloader requirement. > > Signed-off-by: Michal Simek > --- > > --- > arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 ++++++ > arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ > 3 files changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > index 581221fdadf1..719ea5d5ae88 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > @@ -11,30 +11,35 @@ > #include > / { > pss_ref_clk: pss_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <33333333>; > }; > > video_clk: video_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <27000000>; > }; > > pss_alt_ref_clk: pss_alt_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <0>; > }; > > gt_crx_ref_clk: gt_crx_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <108000000>; > }; > > aux_ref_clk: aux_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <27000000>; > @@ -43,6 +48,7 @@ aux_ref_clk: aux_ref_clk { > > &zynqmp_firmware { > zynqmp_clk: clock-controller { > + bootph-all; > #clock-cells = <1>; > compatible = "xlnx,zynqmp-clk"; > clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > index 78ff6a9b3144..8afdf4408a78 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > @@ -243,17 +243,20 @@ tpm@0 { /* slm9670 - U144 */ > > &i2c1 { > status = "okay"; > + bootph-all; > clock-frequency = <400000>; > scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; > sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; > > eeprom: eeprom@50 { /* u46 - also at address 0x58 */ > + bootph-all; > compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ > reg = <0x50>; > /* WP pin EE_WP_EN connected to slg7x644092@68 */ > }; > > eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ > + bootph-all; > compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ > reg = <0x51>; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index d01d4334c95f..51b8349dcacd 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -127,6 +127,7 @@ rproc_1_fw_image: memory@3ef00000 { > }; > > zynqmp_ipi: zynqmp_ipi { > + bootph-all; > compatible = "xlnx,zynqmp-ipi-mailbox"; > interrupt-parent = <&gic>; > interrupts = <0 35 4>; > @@ -136,6 +137,7 @@ zynqmp_ipi: zynqmp_ipi { > ranges; > > ipi_mailbox_pmu1: mailbox@ff9905c0 { > + bootph-all; > reg = <0x0 0xff9905c0 0x0 0x20>, > <0x0 0xff9905e0 0x0 0x20>, > <0x0 0xff990e80 0x0 0x20>, > @@ -152,6 +154,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { > dcc: dcc { > compatible = "arm,dcc"; > status = "disabled"; > + bootph-all; > }; > > pmu { > @@ -177,8 +180,10 @@ zynqmp_firmware: zynqmp-firmware { > compatible = "xlnx,zynqmp-firmware"; > #power-domain-cells = <1>; > method = "smc"; > + bootph-all; > > zynqmp_power: zynqmp-power { > + bootph-all; > compatible = "xlnx,zynqmp-power"; > interrupt-parent = <&gic>; > interrupts = <0 35 4>; > @@ -258,6 +263,7 @@ r5f-1 { > > amba: axi { > compatible = "simple-bus"; > + bootph-all; > #address-cells = <2>; > #size-cells = <2>; > ranges; > @@ -699,6 +705,7 @@ pcie_intc: legacy-interrupt-controller { > }; > > qspi: spi@ff0f0000 { > + bootph-all; > compatible = "xlnx,zynqmp-qspi-1.0"; > status = "disabled"; > clock-names = "ref_clk", "pclk"; > @@ -745,6 +752,7 @@ sata: ahci@fd0c0000 { > }; > > sdhci0: mmc@ff160000 { > + bootph-all; > compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -759,6 +767,7 @@ sdhci0: mmc@ff160000 { > }; > > sdhci1: mmc@ff170000 { > + bootph-all; > compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -851,6 +860,7 @@ ttc3: timer@ff140000 { > }; > > uart0: serial@ff000000 { > + bootph-all; > compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -861,6 +871,7 @@ uart0: serial@ff000000 { > }; > > uart1: serial@ff010000 { > + bootph-all; > compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -982,6 +993,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { > }; > > zynqmp_dpsub: display@fd4a0000 { > + bootph-all; > compatible = "xlnx,zynqmp-dpsub-1.7"; > status = "disabled"; > reg = <0x0 0xfd4a0000 0x0 0x1000>, Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs